Commit 6e495a45 authored by Paul Kocialkowski's avatar Paul Kocialkowski Committed by Tom Rini

omap4: Properly enable USB PHY clocks

This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL
and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value.
Signed-off-by: default avatarPaul Kocialkowski <contact@paulk.fr>
parent 5e56b0a8
......@@ -380,6 +380,10 @@ void enable_basic_clocks(void)
setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
/* Enable 32 KHz clock for USB PHY */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
......
......@@ -129,6 +129,7 @@ struct prcm_regs const omap4_prcm = {
.cm_div_m2_dpll_unipro = 0x4a0081d0,
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
/* cm2.core */
.cm_l3_1_clkstctrl = 0x4a008700,
......
......@@ -134,8 +134,11 @@
/* CM_DSS_DSS_CLKCTRL */
#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
/* CM_L3INIT_USBPHY_CLKCTRL */
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK (1 << 8)
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
......
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