Commit 6fa6035f authored by Anton Staaf's avatar Anton Staaf Committed by Wolfgang Denk
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nios2: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Signed-off-by: default avatarAnton Staaf <>
Cc: Mike Frysinger <>
Cc: Lukasz Majewski <>
Cc: Scott McNutt <>
parent a8fc12eb
......@@ -27,4 +27,15 @@
extern void flush_dcache (unsigned long start, unsigned long size);
extern void flush_icache (unsigned long start, unsigned long size);
* Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
* bytes. If the board configuration has not specified one we default to the
* largest of these values for alignment of DMA buffers.
#endif /* __ASM_NIOS2_CACHE_H_ */
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