Commit 70a4da45 authored by Ralph Kondziella's avatar Ralph Kondziella Committed by John Rigby
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ADS5121 Add PATA support



Original patch from Ralph Kondziella
plus clean up by Wolfgang Denk
plus changes by John Rigby
    use ips clock not lpc
    port forward to current u-boot release
Signed-off-by: default avatarRalph Kondziella <rk@argos-messtechnik.de>
Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
Signed-off-by: default avatarJohn Rigby <jrigby@freescale.com>
parent abfbd0ae
......@@ -31,6 +31,8 @@
#include <i2c.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* Clocks in use */
#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
CLOCK_SCCR1_LPC_EN | \
......@@ -38,6 +40,7 @@
CLOCK_SCCR1_PSCFIFO_EN | \
CLOCK_SCCR1_DDR_EN | \
CLOCK_SCCR1_FEC_EN | \
CLOCK_SCCR1_PATA_EN | \
CLOCK_SCCR1_PCI_EN | \
CLOCK_SCCR1_TPR_EN)
......@@ -326,3 +329,104 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
void init_ide_reset (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
debug ("init_ide_reset\n");
/*
* Clear the reset bit to reset the interface
* cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
*/
immr->pata.pata_ata_control = 0;
udelay(100);
/* Assert the reset bit to enable the interface */
immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
udelay(100);
}
void ide_set_reset (int idereset)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
debug ("ide_set_reset(%d)\n", idereset);
if (idereset) {
immr->pata.pata_ata_control = 0;
udelay(100);
} else {
immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
udelay(100);
}
}
#define CALC_TIMING(t) (t + period - 1) / period
int ide_preinit (void)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
long t;
const struct {
short t0;
short t1;
short t2_8;
short t2_16;
short t2i;
short t4;
short t9;
short tA;
} pio_specs = {
.t0 = 600,
.t1 = 70,
.t2_8 = 290,
.t2_16 = 165,
.t2i = 0,
.t4 = 30,
.t9 = 20,
.tA = 50,
};
union {
u32 config;
struct {
u8 field1;
u8 field2;
u8 field3;
u8 field4;
}bytes;
}cfg;
debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
(u32)&immr->pata);
/* Set the reset bit to 1 to enable the interface */
immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
/* Init timings : we use PIO mode 0 timings */
t = 1000000000 / gd->ips_clk; /* period in ns */
cfg.bytes.field1 = 3;
cfg.bytes.field2 = 3;
cfg.bytes.field3 = (pio_specs.t1 + t) / t;
cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
immr->pata.pata_time1 = cfg.config;
cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
cfg.bytes.field3 = 1;
cfg.bytes.field4 = (pio_specs.t4 + t) / t;
immr->pata.pata_time2 = cfg.config;
cfg.config = immr->pata.pata_time3;
cfg.bytes.field1 = (pio_specs.t9 + t) / t;
immr->pata.pata_time3 = cfg.config;
debug ("PATA preinit complete.\n");
return 0;
}
#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
......@@ -45,6 +45,10 @@
#include <mpc5xxx.h>
#endif
#ifdef CONFIG_MPC512X
#include <mpc512x.h>
#endif
#include <ide.h>
#include <ata.h>
......
......@@ -469,7 +469,34 @@ typedef struct lpc512x {
* PATA
*/
typedef struct pata512x {
u8 fixme[0x100];
/* LOCAL Registers */
u32 pata_time1; /* Time register 1: PIO and tx timing parameter */
u32 pata_time2; /* Time register 2: PIO timing parameter */
u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */
u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */
u32 pata_time5; /* Time register 5: UDMA timing parameter */
u32 pata_time6; /* Time register 6: UDMA timing parameter */
u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */
u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */
u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/
u32 pata_ata_control; /* ATA Interface control register */
u32 pata_irq_pending; /* Interrupt pending register (READONLY) */
u32 pata_irq_enable; /* Interrupt enable register */
u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/
u32 pata_fifo_alarm; /* fifo alarm threshold */
u32 res1[0x1A];
/* DRIVE Registers */
u32 pata_drive_data; /* drive data register*/
u32 pata_drive_features;/* drive features register */
u32 pata_drive_sectcnt; /* drive sector count register */
u32 pata_drive_sectnum; /* drive sector number register */
u32 pata_drive_cyllow; /* drive cylinder low register */
u32 pata_drive_cylhigh; /* drive cylinder high register */
u32 pata_drive_dev_head;/* drive device head register */
u32 pata_drive_command; /* write = drive command, read = drive status reg */
u32 res2[0x06];
u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
u32 res3[0x09];
} pata512x_t;
/*
......
......@@ -355,11 +355,19 @@
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE
#undef CONFIG_CMD_FUSE
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#if defined(CONFIG_CMD_IDE)
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION
#endif /* defined(CONFIG_CMD_IDE) */
/*
* Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
* For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
......@@ -496,4 +504,48 @@
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
/*-----------------------------------------------------------------------
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for IDE not supported */
#define CONFIG_IDE_RESET /* reset for IDE supported */
#define CONFIG_IDE_PREINIT
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC512X_PATA
/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
#define ATA_BASE_ADDR MPC512X_PATA
/*
* Control register bit definitions
*/
#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
#define FSL_ATA_CTRL_IORDY_EN 0x01000000
#endif /* __CONFIG_H */
......@@ -573,6 +573,7 @@ void iopin_initialize(iopin_t *,int);
/* Register Offset Base */
#define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800)
#define MPC512X_PATA (CONFIG_SYS_IMMR + 0x10200)
/* IIM control */
#define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5))
......
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