Commit 743d4815 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Tom Rini

powerpc: mpc85xx: remove P1_P2_RDB boards

These boards are still non-generic boards:
P1011RDB, P1022RDB, P2010RDB, P2020RDB
Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
parent 8d1e3cb1
......@@ -85,11 +85,6 @@ config TARGET_P1022DS
config TARGET_P1023RDB
bool "Support P1023RDB"
config TARGET_P1_P2_RDB
bool "Support P1_P2_RDB"
select SUPPORT_SPL
select SUPPORT_TPL
config TARGET_P1_P2_RDB_PC
bool "Support p1_p2_rdb_pc"
select SUPPORT_SPL
......@@ -184,7 +179,6 @@ source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/p2020come/Kconfig"
......
if TARGET_P1_P2_RDB
config SYS_BOARD
default "p1_p2_rdb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "P1_P2_RDB"
endif
P1_P2_RDB BOARD
#M: -
S: Maintained
F: board/freescale/p1_p2_rdb/
F: include/configs/P1_P2_RDB.h
F: configs/P1011RDB_defconfig
F: configs/P1011RDB_36BIT_defconfig
F: configs/P1011RDB_36BIT_SDCARD_defconfig
F: configs/P1011RDB_36BIT_SPIFLASH_defconfig
F: configs/P1011RDB_NAND_defconfig
F: configs/P1011RDB_SDCARD_defconfig
F: configs/P1011RDB_SPIFLASH_defconfig
F: configs/P1020RDB_defconfig
F: configs/P1020RDB_36BIT_defconfig
F: configs/P1020RDB_36BIT_SDCARD_defconfig
F: configs/P1020RDB_36BIT_SPIFLASH_defconfig
F: configs/P1020RDB_NAND_defconfig
F: configs/P1020RDB_SDCARD_defconfig
F: configs/P1020RDB_SPIFLASH_defconfig
F: configs/P2010RDB_defconfig
F: configs/P2010RDB_36BIT_defconfig
F: configs/P2010RDB_36BIT_SDCARD_defconfig
F: configs/P2010RDB_36BIT_SPIFLASH_defconfig
F: configs/P2010RDB_NAND_defconfig
F: configs/P2010RDB_SDCARD_defconfig
F: configs/P2010RDB_SPIFLASH_defconfig
F: configs/P2020RDB_36BIT_defconfig
F: configs/P2020RDB_36BIT_SDCARD_defconfig
F: configs/P2020RDB_36BIT_SPIFLASH_defconfig
F: configs/P2020RDB_NAND_defconfig
F: configs/P2020RDB_SDCARD_defconfig
F: configs/P2020RDB_SPIFLASH_defconfig
P2020RDB BOARD
M: Poonam Aggrwal <poonam.aggrwal@freescale.com>
S: Maintained
F: configs/P2020RDB_defconfig
#
# Copyright 2009 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
obj-y += spl_minimal.o tlb.o law.o
else
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += p1_p2_rdb.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o
endif
Overview
--------
P2020RDB is a Low End Dual core platform supporting the P2020 processor
of QorIQ series. P2020 is an e500 based dual core SOC.
Building U-boot
-----------
To build the u-boot for P2020RDB:
make P2020RDB_config
make
NOR Flash Banks
-----------
RDB board for P2020 has two flash banks. They are both present on boot.
Booting by default is always from the boot bank at 0xef00_0000.
Memory Map
----------
0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
0xe800_0000 - 0xefff_ffff Boot bank 8MB
0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB
0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB
Switch settings to boot from the NOR flash banks
------------------------------------------------
SW4[8]=0 default NOR Flash bank
SW4[8]=1 Alternate NOR Flash bank
Flashing Images
---------------
To place a new u-boot image in the alternate flash bank and then boot
with that new image temporarily, use this:
tftp 1000000 u-boot.bin
erase ef740000 ef7fffff
cp.b 1000000 ef740000 c0000
Now to boot from the alternate bank change the SW4[8] from 0 to 1.
To program the image in the boot flash bank:
tftp 1000000 u-boot.bin
protect off all
erase eff40000 ffffffff
cp.b 1000000 eff40000 c0000
Using the Device Tree Source File
---------------------------------
To create the DTB (Device Tree Binary) image file,
use a command similar to this:
dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb
Likely, that .dts file will come from here;
linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
Booting Linux
-------------
Place a linux uImage in the TFTP disk area.
tftp 1000000 uImage.p2020rdb
tftp 2000000 rootfs.ext2.gz.uboot
tftp c00000 p2020rdb.dtb
bootm 1000000 2000000 c00000
Implementing AMP(Asymmetric MultiProcessing)
---------------------------------------------
1. Build kernel image for core0:
a. $ make 85xx/p1_p2_rdb_defconfig
b. $ make menuconfig
- un-select "Processor support"->
"Symetric multi-processing support"
c. $ make uImage
d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
2. Build kernel image for core1:
a. $ make 85xx/p1_p2_rdb_defconfig
b. $ make menuconfig
- Un-select "Processor support"->
"Symetric multi-processing support"
- Select "Advanced setup" ->
"Prompt for advanced kernel configuration options"
- Select
"Set physical address where the kernel is loaded"
and set it to 0x20000000, assuming core1 will
start from 512MB.
- Select "Set custom page offset address"
- Select "Set custom kernel base address"
- Select "Set maximum low memory"
- "Exit" and save the selection.
c. $ make uImage
d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
3. Create dtb for core0:
$ dtc -I dts -O dtb -f -b 0
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
/tftpboot/p2020rdb_camp_core0.dtb
4. Create dtb for core1:
$ dtc -I dts -O dtb -f -b 1
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
/tftpboot/p2020rdb_camp_core1.dtb
5. Bring up two cores separately:
a. Power on the board, under u-boot prompt:
=> setenv <serverip>
=> setenv <ipaddr>
=> setenv bootargs root=/dev/ram rw console=ttyS0,115200
b. Bring up core1's kernel first:
=> setenv bootm_low 0x20000000
=> setenv bootm_size 0x10000000
=> tftp 21000000 uImage.core1
=> tftp 22000000 ramdiskfile
=> tftp 20c00000 p2020rdb_camp_core1.dtb
=> interrupts off
=> bootm start 21000000 22000000 20c00000
=> bootm loados
=> bootm ramdisk
=> bootm fdt
=> fdt boardsetup
=> fdt chosen $initrd_start $initrd_end
=> bootm prep
=> cpu 1 release $bootm_low - $fdtaddr -
c. Bring up core0's kernel(on the same u-boot console):
=> setenv bootm_low 0
=> setenv bootm_size 0x20000000
=> tftp 1000000 uImage.core0
=> tftp 2000000 ramdiskfile
=> tftp c00000 p2020rdb_camp_core0.dtb
=> bootm 1000000 2000000 c00000
Please note only core0 will run u-boot, core1 starts kernel directly
after "cpu release" command is issued.
/*
* Copyright 2009, 2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
#define CONFIG_SYS_DDR_RCW_1 0x00000000
#define CONFIG_SYS_DDR_RCW_2 0x00000000
#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
#define CONFIG_SYS_DDR_TIMING_4 0x00000000
#define CONFIG_SYS_DDR_TIMING_5 0x00000000
#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
#define CONFIG_SYS_DDR_MODE_1_400 0x00480432
#define CONFIG_SYS_DDR_MODE_2_400 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
#define CONFIG_SYS_DDR_MODE_1_533 0x00040642
#define CONFIG_SYS_DDR_MODE_2_533 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
phys_size_t fixed_sdram (void)
{
fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
ulong ddr_freq, ddr_freq_mhz;
cpu = gd->arch.cpu;
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#if defined(CONFIG_SYS_RAMBOOT)
return ddr_size;
#endif
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
if(ddr_freq_mhz <= 400)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(ddr_freq_mhz <= 533)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
else if(ddr_freq_mhz <= 667)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
else if(ddr_freq_mhz <= 800)
memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
ddr_cfg_regs.cs[0].bnds = 0x0000001F;
}
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
return ddr_size;
}
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <vsc7385.h>
#include <netdev.h>
#include <rtc.h>
#include <i2c.h>
#include <hwconfig.h>
DECLARE_GLOBAL_DATA_PTR;
#define VSC7385_RST_SET 0x00080000
#define SLIC_RST_SET 0x00040000
#define SGMII_PHY_RST_SET 0x00020000
#define PCIE_RST_SET 0x00010000
#define RGMII_PHY_RST_SET 0x02000000
#define USB_RST_CLR 0x04000000
#define USB2_PORT_OUT_EN 0x01000000
#define GPIO_DIR 0x060f0000
#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \
SGMII_PHY_RST_SET | PCIE_RST_SET | \
RGMII_PHY_RST_SET
#define SYSCLK_MASK 0x00200000
#define BOARDREV_MASK 0x10100000
#define BOARDREV_C 0x00100000
#define BOARDREV_D 0x00000000
#define SYSCLK_66 66666666
#define SYSCLK_100 100000000
unsigned long get_board_sys_clk(ulong dummy)
{
volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
u32 val_gpdat, sysclk_gpio;
val_gpdat = in_be32(&pgpio->gpdat);
sysclk_gpio = val_gpdat & SYSCLK_MASK;
if(sysclk_gpio == 0)
return SYSCLK_66;
else
return SYSCLK_100;
return 0;
}
#ifdef CONFIG_MMC
int board_early_init_f (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr,
(MPC85xx_PMUXCR_SDHC_CD |
MPC85xx_PMUXCR_SDHC_WP));
return 0;
}
#endif
int checkboard (void)
{
u32 val_gpdat, board_rev_gpio;
volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
char board_rev = 0;
struct cpu_type *cpu;
val_gpdat = in_be32(&pgpio->gpdat);
board_rev_gpio = val_gpdat & BOARDREV_MASK;
if (board_rev_gpio == BOARDREV_C)
board_rev = 'C';
else if (board_rev_gpio == BOARDREV_D)
board_rev = 'D';
else
panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
cpu = gd->arch.cpu;
printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
setbits_be32(&pgpio->gpdir, GPIO_DIR);
/*
* Bringing the following peripherals out of reset via GPIOs
* 0 = reset and 1 = out of reset
* GPIO12 - Reset to Ethernet Switch
* GPIO13 - Reset to SLIC/SLAC devices
* GPIO14 - Reset to SGMII_PHY_N
* GPIO15 - Reset to PCIe slots
* GPIO6 - Reset to RGMII PHY
* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
*/
clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
return 0;
}
int misc_init_r(void)
{
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR;
setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
#endif
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned int orig_bus = i2c_get_bus_num();
u8 i2c_data;
i2c_set_bus_num(1);
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
1, &i2c_data, sizeof(i2c_data)) == 0) {
if (i2c_data & 0x2)
puts("NOR Flash Bank : Secondary\n");
else
puts("NOR Flash Bank : Primary\n");
if (i2c_data & 0x1) {
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
puts("SD/MMC : 8-bit Mode\n");
puts("eSPI : Disabled\n");
} else {
puts("SD/MMC : 4-bit Mode\n");
puts("eSPI : Enabled\n");
}
} else {
puts("Failed reading I2C Chip 0x18 on bus 1\n");
}
i2c_set_bus_num(orig_bus);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_16M, 1);
rtc_reset();
return 0;
}
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
char *tmp;
unsigned int vscfw_addr;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
if (is_serdes_configured(SGMII_TSEC3)) {
puts("eTSEC3 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */
if ((tmp = getenv ("vscfw_addr")) != NULL) {
vscfw_addr = simple_strtoul (tmp, NULL, 16);
printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
if (vsc7385_upload_firmware((void *) vscfw_addr,
CONFIG_VSC7385_IMAGE_SIZE))
puts("Failure uploading VSC7385 microcode.\n");
} else
puts("No address specified for VSC7385 microcode.\n");
#endif
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);