Commit 7521af1c authored by Wolfgang Denk's avatar Wolfgang Denk

Add support for AP1000 board.

Patch by James MacAulay, 07 Oct 2005
parent 95f9dda2
......@@ -2,6 +2,9 @@
Changes for U-Boot 1.1.4:
======================================================================
* Add support for AP1000 board.
Patch by James MacAulay, 07 Oct 2005
* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200
Patch by Anders Larsen, 07 Oct 2005
......
......@@ -443,3 +443,8 @@ N: Alex Zuepke
E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
N: James MacAulay
E: james.macaulay@amirix.com
D: Suppport for Amirix AP1000
W: www.amirix.com
......@@ -61,18 +61,18 @@ LIST_8xx=" \
#########################################################################
LIST_4xx=" \
ADCIOP AR405 ASH405 bubinga \
CANBT CPCI2DP CPCI405 CPCI4052 \
CPCI405AB CPCI440 CPCIISER4 CRAYL1 \
csb272 csb472 DASA_SIM DP405 \
DU405 ebony ERIC EXBITGEN \
G2000 HUB405 JSE KAREF \
METROBOX MIP405 MIP405T ML2 \
ml300 ocotea OCRTC ORSG \
PCI405 PIP405 PLU405 PMC405 \
PPChameleonEVB sbc405 VOH405 W7OLMC \
W7OLMG walnut WUH405 XPEDITE1K \
yellowstone yosemite \
ADCIOP AP1000 AR405 ASH405 \
bubinga CANBT CPCI2DP CPCI405 \
CPCI4052 CPCI405AB CPCI440 CPCIISER4 \
CRAYL1 csb272 csb472 DASA_SIM \
DP405 DU405 ebony ERIC \
EXBITGEN G2000 HUB405 JSE \
KAREF METROBOX MIP405 MIP405T \
ML2 ml300 ocotea OCRTC \
ORSG PCI405 PIP405 PLU405 \
PMC405 PPChameleonEVB sbc405 VOH405 \
W7OLMC W7OLMG walnut WUH405 \
XPEDITE1K yellowstone yosemite \
"
#########################################################################
......
......@@ -721,6 +721,9 @@ xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(
ADCIOP_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
AP1000_config:unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ap1000 amirix
APC405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx apc405 esd
......
......@@ -261,44 +261,45 @@ The following options need to be configured:
PowerPC based boards:
---------------------
CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCI405
CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC2
CONFIG_AMX860 CONFIG_GTH CONFIG_PCIPPC6
CONFIG_AR405 CONFIG_gw8260 CONFIG_pcu_e
CONFIG_BAB7xx CONFIG_hermes CONFIG_PIP405
CONFIG_c2mon CONFIG_hymod CONFIG_PM826
CONFIG_CANBT CONFIG_IAD210 CONFIG_ppmc8260
CONFIG_CCM CONFIG_ICU862 CONFIG_QS823
CONFIG_CMI CONFIG_IP860 CONFIG_QS850
CONFIG_cogent_mpc8260 CONFIG_IPHASE4539 CONFIG_QS860T
CONFIG_cogent_mpc8xx CONFIG_IVML24 CONFIG_RBC823
CONFIG_CPCI405 CONFIG_IVML24_128 CONFIG_RPXClassic
CONFIG_CPCI4052 CONFIG_IVML24_256 CONFIG_RPXlite
CONFIG_CPCIISER4 CONFIG_IVMS8 CONFIG_RPXsuper
CONFIG_CPU86 CONFIG_IVMS8_128 CONFIG_rsdproto
CONFIG_CRAYL1 CONFIG_IVMS8_256 CONFIG_sacsng
CONFIG_CSB272 CONFIG_JSE CONFIG_Sandpoint8240
CONFIG_CU824 CONFIG_LANTEC CONFIG_Sandpoint8245
CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8260
CONFIG_DB64360 CONFIG_MBX CONFIG_sbc8560
CONFIG_DB64460 CONFIG_MBX860T CONFIG_SM850
CONFIG_DU405 CONFIG_MHPC CONFIG_SPD823TS
CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_STXGP3
CONFIG_EBONY CONFIG_MOUSSE CONFIG_SXNI855T
CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM823L
CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM8260
CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM850L
CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM855L
CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TQM860L
CONFIG_ETX094 CONFIG_MVS1 CONFIG_TTTech
CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_UTX8245
CONFIG_FADS823 CONFIG_NETTA CONFIG_V37
CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMC
CONFIG_FADS860T CONFIG_NX823 CONFIG_W7OLMG
CONFIG_FLAGADM CONFIG_OCRTC CONFIG_WALNUT
CONFIG_FPS850L CONFIG_ORSG CONFIG_ZPC1900
CONFIG_FPS860L CONFIG_OXC CONFIG_ZUMA
CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCIPPC2
CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC6
CONFIG_AMX860 CONFIG_GTH CONFIG_pcu_e
CONFIG_AP1000 CONFIG_gw8260 CONFIG_PIP405
CONFIG_AR405 CONFIG_hermes CONFIG_PM826
CONFIG_BAB7xx CONFIG_hymod CONFIG_ppmc8260
CONFIG_c2mon CONFIG_IAD210 CONFIG_QS823
CONFIG_CANBT CONFIG_ICU862 CONFIG_QS850
CONFIG_CCM CONFIG_IP860 CONFIG_QS860T
CONFIG_CMI CONFIG_IPHASE4539 CONFIG_RBC823
CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RPXClassic
CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXlite
CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXsuper
CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_rsdproto
CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_sacsng
CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_Sandpoint8240
CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8245
CONFIG_CSB272 CONFIG_LANTEC CONFIG_sbc8260
CONFIG_CU824 CONFIG_lwmon CONFIG_sbc8560
CONFIG_DASA_SIM CONFIG_MBX CONFIG_SM850
CONFIG_DB64360 CONFIG_MBX860T CONFIG_SPD823TS
CONFIG_DB64460 CONFIG_MHPC CONFIG_STXGP3
CONFIG_DU405 CONFIG_MIP405 CONFIG_SXNI855T
CONFIG_DUET_ADS CONFIG_MOUSSE CONFIG_TQM823L
CONFIG_EBONY CONFIG_MPC8260ADS CONFIG_TQM8260
CONFIG_ELPPC CONFIG_MPC8540ADS CONFIG_TQM850L
CONFIG_ELPT860 CONFIG_MPC8540EVAL CONFIG_TQM855L
CONFIG_ep8260 CONFIG_MPC8560ADS CONFIG_TQM860L
CONFIG_ERIC CONFIG_MUSENKI CONFIG_TTTech
CONFIG_ESTEEM192E CONFIG_MVS1 CONFIG_UTX8245
CONFIG_ETX094 CONFIG_NETPHONE CONFIG_V37
CONFIG_EVB64260 CONFIG_NETTA CONFIG_W7OLMC
CONFIG_FADS823 CONFIG_NETVIA CONFIG_W7OLMG
CONFIG_FADS850SAR CONFIG_NX823 CONFIG_WALNUT
CONFIG_FADS860T CONFIG_OCRTC CONFIG_ZPC1900
CONFIG_FLAGADM CONFIG_ORSG CONFIG_ZUMA
CONFIG_FPS850L CONFIG_OXC
CONFIG_FPS860L CONFIG_PCI405
ARM based boards:
-----------------
......
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
This diff is collapsed.
/*
* ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally
*
* Author : James MacAulay
*
* This software may be used and distributed according to the terms of
* the GNU General Public License (GPL) version 2, incorporated herein by
* reference. Drivers based on or derived from this code fall under the GPL
* and must retain the authorship, copyright and this license notice. This
* file is not a complete program and may only be used when the entire
* program is licensed under the GPL.
*
*/
#ifndef __AP1000_H
#define __AP1000_H
/*
* Revision Register stuff
*/
#define AP1xx_FPGA_REV_ADDR 0x29000000
#define AP1xx_PLATFORM_MASK 0xFF000000
#define AP100_BASELINE_PLATFORM 0x01000000
#define AP1xx_QUADGE_PLATFORM 0x02000000
#define AP1xx_MGT_REF_PLATFORM 0x03000000
#define AP1xx_STANDARD_PLATFORM 0x04000000
#define AP1xx_DUAL_PLATFORM 0x05000000
#define AP1xx_BASE_SRAM_PLATFORM 0x06000000
#define AP1000_BASELINE_PLATFORM 0x21000000
#define AP1xx_TESTPLATFORM_MASK 0xC0000000
#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000
#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000
#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000
#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000
#define AP1xx_TARGET_MASK 0x00FF0000
#define AP1xx_AP107_TARGET 0x00010000
#define AP1xx_AP120_TARGET 0x00020000
#define AP1xx_AP130_TARGET 0x00030000
#define AP1xx_AP1070_TARGET 0x00040000
#define AP1xx_AP1100_TARGET 0x00050000
#define AP1xx_UNKNOWN_STR "Unknown"
#define AP1xx_PLATFORM_STR " Platform"
#define AP1xx_BASELINE_PLATFORM_STR "Baseline"
#define AP1xx_QUADGE_PLATFORM_STR "Quad GE"
#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference"
#define AP1xx_STANDARD_PLATFORM_STR "Standard"
#define AP1xx_DUAL_PLATFORM_STR "Dual"
#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM"
#define AP1xx_TESTPLATFORM_STR " Test Platform"
#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base"
#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine"
#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine"
#define AP1xx_TARGET_STR " Board"
#define AP1xx_AP107_TARGET_STR "AP107"
#define AP1xx_AP120_TARGET_STR "AP120"
#define AP1xx_AP130_TARGET_STR "AP130"
#define AP1xx_AP1070_TARGET_STR "AP1070"
#define AP1xx_AP1100_TARGET_STR "AP1100"
/*
* Flash Stuff
*/
#define AP1xx_PROGRAM_FLASH_INDEX 0
#define AP1xx_CONFIG_FLASH_INDEX 1
/*
* System Ace Stuff
*/
#define AP1000_SYSACE_REGBASE 0x28000000
#define SYSACE_STATREG0 0x04 // 7:0
#define SYSACE_STATREG1 0x05 // 15:8
#define SYSACE_STATREG2 0x06 // 23:16
#define SYSACE_STATREG3 0x07 // 31:24
#define SYSACE_ERRREG0 0x08 // 7:0
#define SYSACE_ERRREG1 0x09 // 15:8
#define SYSACE_ERRREG2 0x0a // 23:16
#define SYSACE_ERRREG3 0x0b // 31:24
#define SYSACE_CTRLREG0 0x18 // 7:0
#define SYSACE_CTRLREG1 0x19 // 15:8
#define SYSACE_CTRLREG2 0x1A // 23:16
#define SYSACE_CTRLREG3 0x1B // 31:24
/*
* Software reconfig thing
*/
#define SW_BYTE_SECTOR_ADDR 0x24FE0000
#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF
#define SW_BYTE_SECTOR_SIZE 0x00020000
#define SW_BYTE_MASK 0x00000003
#define DEFAULT_TEMP_ADDR 0x00100000
#define AP1000_CPLD_BASE 0x26000000
/* PowerSpan II Stuff */
#define PSII_SYNC() asm("eieio")
#define PSPAN_BASEADDR 0x30000000
#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \
0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
0x0, /* Byte 4 - Powerspan reserved - start of short load */ \
0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \
0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \
0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
0x00, /* Byte 15 - Vital Product Data Disabled. */ \
0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \
0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
0x00, /* Byte 18 - I2O disabled */ \
0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \
0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \
0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
/* Long Load Information */ \
0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
0x01, /* Byte 39 - Power span revision 1. */ \
0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \
0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
0x01, /* Byte 59 - PCI-2 class revision 1 */ \
0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
#define EEPROM_LENGTH 64 /* Long Load */
#define I2C_SENSOR_DEV 0x9
#define I2C_SENSOR_CHIP_SEL 0x4
/*
* Board Functions
*/
void set_eat_machine_checks(int a_flag);
int get_eat_machine_checks(void);
unsigned int get_platform(void);
unsigned int get_device(void);
void* memcpyb(void * dest,const void *src,size_t count);
int process_bootflag(ulong bootflag);
void user_led_on(void);
void user_led_off(void);
#endif /* __COMMON_H_ */
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Start at bottom of RAM, but at an aliased address so that it looks
# like it's not in RAM. This is a bit of voodoo to allow it to be
# run from RAM instead of Flash.
TEXT_BASE = 0x08000000
This diff is collapsed.
/*
* init.S: Stubs for ppcboot initialization
*
* Copyright 2002 Mind NV
*
* http://www.mind.be/
*
* Author : Peter De Schrijver (p2@mind.be)
*
* This software may be used and distributed according to the terms of
* the GNU General Public License (GPL) version 2, incorporated herein by
* reference. Drivers based on or derived from this code fall under the GPL
* and must retain the authorship, copyright and this license notice. This
* file is not a complete program and may only be used when the entire
* program is licensed under the GPL.
*
*/
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
.globl sdram_init
sdram_init:
blr
This diff is collapsed.
This diff is collapsed.
/**
* @file powerspan.h Header file for PowerSpan II code.
*/
/*
* (C) Copyright 2005
* AMIRIX Systems Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef POWERSPAN_H
#define POWERSPAN_H
#define CLEAR_MASTER_ABORT 0xdeadbeef
#define NO_DEVICE_FOUND -1
#define ILLEGAL_REG_OFFSET -2
#define I2C_BUSY -3
#define I2C_ERR -4
#define REG_P1_CSR 0x004
#define REGS_P1_BST 0x018
#define REG_P1_ERR_CSR 0x150
#define REG_P1_MISC_CSR 0x160
#define REGS_P1_TGT_CSR 0x100
#define REGS_P1_TGT_TADDR 0x104
#define REGS_PB_SLAVE_CSR 0x200
#define REGS_PB_SLAVE_TADDR 0x204
#define REGS_PB_SLAVE_BADDR 0x208
#define REG_CONFIG_ADDRESS 0x290
#define REG_CONFIG_DATA 0x294
#define REG_PB_ERR_CSR 0x2B0
#define REG_PB_MISC_CSR 0x2C0
#define REG_MISC_CSR 0x400
#define REG_I2C_CSR 0x408
#define REG_RESET_CSR 0x40C
#define REG_ISR0 0x410
#define REG_ISR1 0x414
#define REG_IER0 0x418
#define REG_MBOX_MAP 0x420
#define REG_HW_MAP 0x42C
#define REG_IDR 0x444
#define CSR_MEMORY_SPACE_ENABLE 0x00000002
#define CSR_PCI_MASTER_ENABLE 0x00000004
#define P1_BST_OFF 0x04
#define PX_ERR_ERR_STATUS 0x01000000
#define PX_MISC_CSR_MAX_RETRY_MASK 0x00000F00
#define PX_MISC_CSR_MAX_RETRY 0x00000F00
#define PX_MISC_REG_BAR_ENABLE 0x00008000
#define PB_MISC_TEA_ENABLE 0x00000010
#define PB_MISC_MAC_TEA 0x00000040
#define P1_TGT_IMAGE_OFF 0x010
#define PX_TGT_CSR_IMG_EN 0x80000000
#define PX_TGT_CSR_TA_EN 0x40000000
#define PX_TGT_CSR_BAR_EN 0x20000000
#define PX_TGT_CSR_MD_EN 0x10000000
#define PX_TGT_CSR_MODE 0x00800000
#define PX_TGT_CSR_DEST 0x00400000
#define PX_TGT_CSR_MEM_IO 0x00200000
#define PX_TGT_CSR_GBL 0x00080000
#define PX_TGT_CSR_CL 0x00040000
#define PX_TGT_CSR_PRKEEP 0x00000080
#define PX_TGT_CSR_BS_MASK 0x0F000000
#define PX_TGT_MEM_IO 0x00200000
#define PX_TGT_CSR_RTT_MASK 0x001F0000
#define PX_TGT_CSR_RTT_READ 0x000A0000
#define PX_TGT_CSR_WTT_MASK 0x00001F00
#define PX_TGT_CSR_WTT_WFLUSH 0x00000200
#define PX_TGT_CSR_END_MASK 0x00000060
#define PX_TGT_CSR_BIG_END 0x00000040
#define PX_TGT_CSR_TRUE_LEND 0x00000060
#define PX_TGT_CSR_RDAMT_MASK 0x00000007
#define PX_TGT_CSR_BS_64MB 0xa
#define PX_TGT_CSR_BS_16MB 0x8
#define PX_TGT_USE_MEM_IO 1
#define PX_TGT_NOT_MEM_IO 0
#define PB_SLAVE_IMAGE_OFF 0x010
#define PB_SLAVE_CSR_IMG_EN 0x80000000
#define PB_SLAVE_CSR_TA_EN 0x40000000
#define PB_SLAVE_CSR_MD_EN 0x20000000
#define PB_SLAVE_CSR_MODE 0x00800000
#define PB_SLAVE_CSR_DEST 0x00400000
#define PB_SLAVE_CSR_MEM_IO 0x00200000
#define PB_SLAVE_CSR_PRKEEP 0x00000080
#define PB_SLAVE_CSR_BS_MASK 0x1F000000
#define PB_SLAVE_CSR_END_MASK 0x00000060
#define PB_SLAVE_CSR_BIG_END 0x00000040
#define PB_SLAVE_CSR_TRUE_LEND 0x00000060
#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007
#define PB_SLAVE_USE_MEM_IO 1
#define PB_SLAVE_NOT_MEM_IO 0
#define MISC_CSR_PCI1_LOCK 0x00000080
#define I2C_CSR_ADDR 0xFF000000 /* Specifies I2C Device Address to be Accessed */
#define I2C_CSR_DATA 0x00FF0000 /* Specifies the Required Data for a Write */
#define I2C_CSR_DEV_CODE 0x0000F000 /* Device Select. I2C 4-bit Device Code */
#define I2C_CSR_CS 0x00000E00 /* Chip Select */
#define I2C_CSR_RW 0x00000100 /* Read/Write */
#define I2C_CSR_ACT 0x00000080 /* I2C Interface Active */
#define I2C_CSR_ERR 0x00000040 /* Error */
#define I2C_EEPROM_DEV 0xa
#define I2C_EEPROM_CHIP_SEL 0
#define I2C_READ 0
#define I2C_WRITE 1
#define RESET_CSR_EEPROM_LOAD 0x00000010
#define ISR_CLEAR_ALL 0xFFFFFFFF
#define IER0_DMA_INTS_EN 0x0F000000
#define IER0_PCI_1_EN 0x00400000
#define IER0_HW_INTS_EN 0x003F0000
#define IER0_MB_INTS_EN 0x000000FF
#define IER0_DEFAULT (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN)
#define MBOX_MAP_TO_INT4 0xCCCCCCCC
#define HW_MAP_HW4_TO_INT4 0x000C0000
#define IDR_PCI_A_OUT 0x40000000
#define IDR_MBOX_OUT 0x10000000
int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val);
int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val);
int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val);
int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val);
int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val);
int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val);
unsigned int PowerSpanRead(unsigned int theOffset);
void PowerSpanWrite(unsigned int theOffset, unsigned int theValue);
int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag);
int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val);
int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val);
int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
#endif
/*
* (C) Copyright 2002
* Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <asm/u-boot.h>
#include <asm/processor.h>
#include <common.h>
#include <command.h>
#include <config.h>
#include <ns16550.h>
#if 0
#include "serial.h"
#endif
const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
#undef CFG_DUART_CHAN
#define CFG_DUART_CHAN gComPort
static int gComPort = 0;
int
serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
(void)NS16550_init(COM_PORTS[0], clock_divisor);
gComPort = 0;
return 0;
}
void
serial_putc(const char c)
{
if (c == '\n'){
NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r');
}
NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c);
}
int
serial_getc(void)
{
return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]);
}
int
serial_tstc(void)
{
return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]);
}
void
serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
#ifdef CFG_INIT_CHAN1
NS16550_reinit(COM_PORTS[0], clock_divisor);
#endif
#ifdef CFG_INIT_CHAN2
NS16550_reinit(COM_PORTS[1], clock_divisor);
#endif
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
void
kgdb_serial_init(void)
{
}
void
putDebugChar (int c)
{
serial_putc (c);
}
void
putDebugStr (const char *str)
{
serial_puts (str);
}
int
getDebugChar (void)
{
return serial_getc();
}
void
kgdb_interruptible (int yes)
{
return;
}
#endif /* CFG_CMD_KGDB */