Commit 7588bf93 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

parents 36737f22 950f86ca
......@@ -43,6 +43,7 @@ config SYS_CONFIG_NAME
config BOOT_INIT_FILE
string "boot.bin init register filename"
depends on SPL
default ""
help
Add register writes to boot.bin format (max 256 pairs).
......
......@@ -16,7 +16,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
......@@ -30,7 +30,7 @@
>;
};
cpu@1 {
cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
......
......@@ -7,6 +7,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
......
......@@ -18,8 +18,6 @@
#define ARASAN_NAND_BASEADDR 0xFF100000
#define ZYNQMP_SATA_BASEADDR 0xFD0C0000
#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
......
......@@ -124,121 +124,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
}
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
/*
* fdt_get_reg - Fill buffer by information from DT
*/
static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
const u32 *cell, int n)
{
int i = 0, b, banks;
int parent_offset = fdt_parent_offset(fdt, nodeoffset);
int address_cells = fdt_address_cells(fdt, parent_offset);
int size_cells = fdt_size_cells(fdt, parent_offset);
char *p = buf;
u64 val;
u64 vals;
debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
__func__, address_cells, size_cells, buf, cell);
/* Check memory bank setup */
banks = n % (address_cells + size_cells);
if (banks)
panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
n, address_cells, size_cells);
banks = n / (address_cells + size_cells);
for (b = 0; b < banks; b++) {
debug("%s: Bank #%d:\n", __func__, b);
if (address_cells == 2) {
val = cell[i + 1];
val <<= 32;
val |= cell[i];
val = fdt64_to_cpu(val);
debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
__func__, val, p, &cell[i]);
*(phys_addr_t *)p = val;
} else {
debug("%s: addr32=%x, ptr=%p\n",
__func__, fdt32_to_cpu(cell[i]), p);
*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
}
p += sizeof(phys_addr_t);
i += address_cells;
debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
sizeof(phys_addr_t));
if (size_cells == 2) {
vals = cell[i + 1];
vals <<= 32;
vals |= cell[i];
vals = fdt64_to_cpu(vals);
debug("%s: size64=%llx, ptr=%p, cell=%p\n",
__func__, vals, p, &cell[i]);
*(phys_size_t *)p = vals;
} else {
debug("%s: size32=%x, ptr=%p\n",
__func__, fdt32_to_cpu(cell[i]), p);
*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
}
p += sizeof(phys_size_t);
i += size_cells;
debug("%s: ps=%p, i=%x, size=%zu\n",
__func__, p, i, sizeof(phys_size_t));
}
/* Return the first address size */
return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
}
#define FDT_REG_SIZE sizeof(u32)
/* Temp location for sharing data for storing */
/* Up to 64-bit address + 64-bit size */
static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
void dram_init_banksize(void)
{
int bank;
memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
debug("Bank #%d: start %llx\n", bank,
(unsigned long long)gd->bd->bi_dram[bank].start);
debug("Bank #%d: size %llx\n", bank,
(unsigned long long)gd->bd->bi_dram[bank].size);
}
fdtdec_setup_memory_banksize();
}
int dram_init(void)
{
int node, len;
const void *blob = gd->fdt_blob;
const u32 *cell;
memset(&tmp, 0, sizeof(tmp));
/* find or create "/memory" node. */
node = fdt_subnode_offset(blob, 0, "memory");
if (node < 0) {
printf("%s: Can't get memory node\n", __func__);
return node;
}
/* Get pointer to cells and lenght of it */
cell = fdt_getprop(blob, node, "reg", &len);
if (!cell) {
printf("%s: Can't get reg property\n", __func__);
return -1;
}
gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
zynq_ddrc_init();
......
......@@ -180,121 +180,15 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
}
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
/*
* fdt_get_reg - Fill buffer by information from DT
*/
static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
const u32 *cell, int n)
{
int i = 0, b, banks;
int parent_offset = fdt_parent_offset(fdt, nodeoffset);
int address_cells = fdt_address_cells(fdt, parent_offset);
int size_cells = fdt_size_cells(fdt, parent_offset);
char *p = buf;
u64 val;
u64 vals;
debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
__func__, address_cells, size_cells, buf, cell);
/* Check memory bank setup */
banks = n % (address_cells + size_cells);
if (banks)
panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
n, address_cells, size_cells);
banks = n / (address_cells + size_cells);
for (b = 0; b < banks; b++) {
debug("%s: Bank #%d:\n", __func__, b);
if (address_cells == 2) {
val = cell[i + 1];
val <<= 32;
val |= cell[i];
val = fdt64_to_cpu(val);
debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
__func__, val, p, &cell[i]);
*(phys_addr_t *)p = val;
} else {
debug("%s: addr32=%x, ptr=%p\n",
__func__, fdt32_to_cpu(cell[i]), p);
*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
}
p += sizeof(phys_addr_t);
i += address_cells;
debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
sizeof(phys_addr_t));
if (size_cells == 2) {
vals = cell[i + 1];
vals <<= 32;
vals |= cell[i];
vals = fdt64_to_cpu(vals);
debug("%s: size64=%llx, ptr=%p, cell=%p\n",
__func__, vals, p, &cell[i]);
*(phys_size_t *)p = vals;
} else {
debug("%s: size32=%x, ptr=%p\n",
__func__, fdt32_to_cpu(cell[i]), p);
*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
}
p += sizeof(phys_size_t);
i += size_cells;
debug("%s: ps=%p, i=%x, size=%zu\n",
__func__, p, i, sizeof(phys_size_t));
}
/* Return the first address size */
return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
}
#define FDT_REG_SIZE sizeof(u32)
/* Temp location for sharing data for storing */
/* Up to 64-bit address + 64-bit size */
static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
void dram_init_banksize(void)
{
int bank;
memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
debug("Bank #%d: start %llx\n", bank,
(unsigned long long)gd->bd->bi_dram[bank].start);
debug("Bank #%d: size %llx\n", bank,
(unsigned long long)gd->bd->bi_dram[bank].size);
}
fdtdec_setup_memory_banksize();
}
int dram_init(void)
{
int node, len;
const void *blob = gd->fdt_blob;
const u32 *cell;
memset(&tmp, 0, sizeof(tmp));
/* find or create "/memory" node. */
node = fdt_subnode_offset(blob, 0, "memory");
if (node < 0) {
printf("%s: Can't get memory node\n", __func__);
return node;
}
/* Get pointer to cells and lenght of it */
cell = fdt_getprop(blob, node, "reg", &len);
if (!cell) {
printf("%s: Can't get reg property\n", __func__);
return -1;
}
gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
return 0;
}
......@@ -311,17 +205,6 @@ void reset_cpu(ulong addr)
{
}
#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
#if defined(CONFIG_SATA_CEVA)
init_sata(0);
#endif
ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
scsi_scan(1);
}
#endif
int board_late_init(void)
{
u32 reg = 0;
......
......@@ -620,7 +620,7 @@ static int initr_ambapp_print(void)
}
#endif
#if defined(CONFIG_SCSI)
#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
static int initr_scsi(void)
{
puts("SCSI: ");
......@@ -923,7 +923,7 @@ init_fnc_t init_sequence_r[] = {
initr_ambapp_print,
#endif
#endif
#ifdef CONFIG_SCSI
#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
INIT_FUNC_WATCHDOG_RESET
initr_scsi,
#endif
......
......@@ -1375,11 +1375,10 @@ int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
img_len, BIT_PARTIAL);
}
printf(" Programming %s bitstream... ", name);
if (err)
printf("failed\n");
else
printf("OK\n");
return err;
printf(" Programming %s bitstream... OK\n", name);
break;
default:
printf("The given image format is not supported (corrupt?)\n");
......
......@@ -107,6 +107,18 @@ int mdio_register(struct mii_dev *bus)
return 0;
}
int mdio_register_seq(struct mii_dev *bus, int seq)
{
int ret;
/* Setup a unique name for each mdio bus */
ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq);
if (ret < 0)
return ret;
return mdio_register(bus);
}
int mdio_unregister(struct mii_dev *bus)
{
if (!bus)
......
......@@ -10,7 +10,10 @@
#include <inttypes.h>
#include <pci.h>
#include <scsi.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#if !defined(CONFIG_DM_SCSI)
#ifdef CONFIG_SCSI_DEV_LIST
#define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST
#else
......@@ -31,6 +34,7 @@
#endif
#define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
#endif
#endif
#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT)
const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST };
......@@ -39,11 +43,13 @@ static ccb tempccb; /* temporary scsi command buffer */
static unsigned char tempbuff[512]; /* temporary data buffer */
#if !defined(CONFIG_DM_SCSI)
static int scsi_max_devs; /* number of highest available scsi device */
static int scsi_curr_dev; /* current device */
static struct blk_desc scsi_dev_desc[CONFIG_SYS_SCSI_MAX_DEVICE];
#endif
/* almost the maximum amount of the scsi_ext command.. */
#define SCSI_MAX_READ_BLK 0xFFFF
......@@ -444,6 +450,7 @@ static void scsi_init_dev_desc_priv(struct blk_desc *dev_desc)
#endif
}
#if !defined(CONFIG_DM_SCSI)
/**
* scsi_init_dev_desc - initialize all SCSI specific blk_desc properties
*
......@@ -460,6 +467,7 @@ static void scsi_init_dev_desc(struct blk_desc *dev_desc, int devnum)
scsi_init_dev_desc_priv(dev_desc);
}
#endif
/**
* scsi_detect_dev - Detect scsi device
......@@ -540,6 +548,73 @@ removable:
* (re)-scan the scsi bus and reports scsi device info
* to the user if mode = 1
*/
#if defined(CONFIG_DM_SCSI)
int scsi_scan(int mode)
{
unsigned char i, lun;
struct uclass *uc;
struct udevice *dev; /* SCSI controller */
int ret;
if (mode == 1)
printf("scanning bus for devices...\n");
ret = uclass_get(UCLASS_SCSI, &uc);
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
struct scsi_platdata *plat; /* scsi controller platdata */
/* probe SCSI controller driver */
ret = device_probe(dev);
if (ret)
return ret;
/* Get controller platdata */
plat = dev_get_platdata(dev);
for (i = 0; i < plat->max_id; i++) {
for (lun = 0; lun < plat->max_lun; lun++) {
struct udevice *bdev; /* block device */
/* block device description */
struct blk_desc *bdesc;
char str[10];
/*
* Create only one block device and do detection
* to make sure that there won't be a lot of
* block devices created
*/
snprintf(str, sizeof(str), "id%dlun%d", i, lun);
ret = blk_create_devicef(dev, "scsi_blk",
str, IF_TYPE_SCSI,
-1, 0, 0, &bdev);
if (ret) {
debug("Can't create device\n");
return ret;
}
bdesc = dev_get_uclass_platdata(bdev);
scsi_init_dev_desc_priv(bdesc);
bdesc->lun = lun;
ret = scsi_detect_dev(i, bdesc);
if (ret) {
device_unbind(bdev);
continue;
}
if (mode == 1) {
printf(" Device %d: ", 0);
dev_print(bdesc);
} /* if mode */
} /* next LUN */
}
}
return 0;
}
#else
int scsi_scan(int mode)
{
unsigned char i, lun;
......@@ -576,6 +651,7 @@ int scsi_scan(int mode)
#endif
return 0;
}
#endif
#ifdef CONFIG_BLK
static const struct blk_ops scsi_blk_ops = {
......
......@@ -42,6 +42,8 @@ CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
......
......@@ -34,6 +34,8 @@ CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
......
......@@ -34,6 +34,8 @@ CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_DFU_RAM=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
......
......@@ -19,6 +19,15 @@ config AHCI
operations at present. The block device interface has not been converted
to driver model.
config DM_SCSI
bool "Support SCSI controllers with driver model"
depends on BLK
help
This option enables the SCSI (Small Computer System Interface) uclass
which supports SCSI and SATA HDDs. For every device configuration
(IDs/LUNs) a block device is created with RAW read/write and
filesystem support.
config BLOCK_CACHE
bool "Use block device cache"
default n
......@@ -27,3 +36,16 @@ config BLOCK_CACHE
This is most useful when accessing filesystems under U-Boot since
it will prevent repeated reads from directory structures and other
filesystem data structures.
menu "SATA/SCSI device support"
config SATA_CEVA
bool "Ceva Sata controller"
depends on AHCI
depends on DM_SCSI
help
This option enables Ceva Sata controller hard IP available on Xilinx
ZynqMP. Support up to 2 external devices. Complient with SATA 3.1 and
AHCI 1.3 specifications with hot-plug detect feature.
endmenu
......@@ -12,6 +12,7 @@ obj-y += blk_legacy.o
endif
obj-$(CONFIG_AHCI) += ahci-uclass.o
obj-$(CONFIG_DM_SCSI) += scsi-uclass.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
......
......@@ -168,7 +168,7 @@ int ahci_reset(void __iomem *base)
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
# ifdef CONFIG_DM_PCI
struct udevice *dev = probe_ent->dev;
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
......@@ -198,7 +198,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
writel(cap_save, mmio + HOST_CAP);
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
#ifndef CONFIG_SCSI_AHCI_PLAT
#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
# ifdef CONFIG_DM_PCI
if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
u16 tmp16;
......@@ -327,6 +327,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
#if !defined(CONFIG_DM_SCSI)
#ifndef CONFIG_SCSI_AHCI_PLAT
# ifdef CONFIG_DM_PCI
dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
......@@ -337,6 +338,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
tmp |= PCI_COMMAND_MASTER;
pci_write_config_word(pdev, PCI_COMMAND, tmp16);
# endif
#endif
#endif
return 0;
}
......@@ -344,8 +346,8 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
# ifdef CONFIG_DM_PCI
#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
# if defined(CONFIG_DM_PCI)
struct udevice *dev = probe_ent->dev;
# else
pci_dev_t pdev = probe_ent->dev;
......@@ -372,7 +374,7 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent)
else
speed_s = "?";
#ifdef CONFIG_SCSI_AHCI_PLAT
#if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
scc_s = "SATA";
#else
# ifdef CONFIG_DM_PCI
......@@ -424,13 +426,15 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent)
}
#ifndef CONFIG_SCSI_AHCI_PLAT
# ifdef CONFIG_DM_PCI
# if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
static int ahci_init_one(struct udevice *dev)
# else
static int ahci_init_one(pci_dev_t dev)
# endif
{
#if !defined(CONFIG_DM_SCSI)
u16 vendor;
#endif
int rc;
probe_ent = malloc(sizeof(struct ahci_probe_ent));
......@@ -450,6 +454,7 @@ static int ahci_init_one(pci_dev_t dev)
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
#if !defined(CONFIG_DM_SCSI)
#ifdef CONFIG_DM_PCI
probe_ent->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
PCI_REGION_MEM);
......@@ -473,6 +478,10 @@ static int ahci_init_one(pci_dev_t dev)
if (vendor == 0x197b)
pci_write_config_byte(dev, 0x41, 0xa1);
#endif
#else
struct scsi_platdata *plat = dev_get_platdata(dev);
probe_ent->mmio_base = (void *)plat->base;
#endif
debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
/* initialize adapter */
......@@ -954,14 +963,17 @@ int scsi_exec(ccb *pccb)
}
#if defined(CONFIG_DM_SCSI)
void scsi_low_level_init(int busdevfunc, struct udevice *dev)
#else
void scsi_low_level_init(int busdevfunc)
#endif
{
int i;
u32 linkmap;
#ifndef CONFIG_SCSI_AHCI_PLAT
# ifdef CONFIG_DM_PCI
# if defined(CONFIG_DM_PCI)
struct udevice *dev;
int ret;
......@@ -969,6 +981,8 @@ void scsi_low_level_init(int busdevfunc)
if (ret)
return;
ahci_init_one(dev);
# elif defined(CONFIG_DM_SCSI)
ahci_init_one(dev);
# else
ahci_init_one(busdevfunc);
# endif
......
......@@ -26,7 +26,7 @@ static const char *if_typename_str[IF_TYPE_COUNT] = {
static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = {
[IF_TYPE_IDE] = UCLASS_INVALID,
[IF_TYPE_SCSI] = UCLASS_INVALID,
[IF_TYPE_SCSI] = UCLASS_SCSI,
[IF_TYPE_ATAPI] = UCLASS_INVALID,
[IF_TYPE_USB] = UCLASS_MASS_STORAGE,
[IF_TYPE_DOC] = UCLASS_INVALID,
......
......@@ -5,6 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <netdev.h>
#include <ahci.h>
#include <scsi.h>
......@@ -73,10 +74,9 @@
#define DRV_NAME "ahci-ceva"
#define CEVA_FLAG_BROKEN_GEN2 1
int init_sata(int dev)
static int ceva_init_sata(ulong mmio)
{
ulong tmp;
ulong mmio = ZYNQMP_SATA_BASEADDR;
int i;
/*
......@@ -111,3 +111,40 @@ int init_sata(int dev)
}
return 0;
}
static int sata_ceva_probe(struct udevice *dev)
{
struct scsi_platdata *plat = dev_get_platdata(dev);
ceva_init_sata(plat->base);
return 0;
}
static const struct udevice_id sata_ceva_ids[] = {
{ .compatible = "ceva,ahci-1v84" },
{ }
};
static int sata_ceva_ofdata_to_platdata(struct udevice *dev)