Commit 76b40ab4 authored by Tom Rini's avatar Tom Rini

Merge u-boot/master into u-boot-ti/master

In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850).  Resolve these
conflicts manually and comment the #else/#endif lines for clarity.

Conflicts:
	arch/arm/include/asm/arch-davinci/gpio.h
	drivers/gpio/da8xx_gpio.c
Signed-off-by: default avatarTom Rini <trini@ti.com>
parents de62688b fc959081
......@@ -1227,7 +1227,7 @@ Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
# Board CPU #
#########################################################################
Mike Frysinger <vapier@gentoo.org>
Sonic Zhang <sonic.adi@gmail.com>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF506F-EZKIT BF506
......@@ -1244,6 +1244,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF538F-EZKIT BF538
BF548-EZKIT BF548
BF561-EZKIT BF561
BF609-EZKIT BF609
M.Hasewinkel (MHA) <info@ssv-embedded.de>
......
......@@ -35,6 +35,9 @@ usage()
Environment variables:
BUILD_NCPUS number of parallel make jobs (default: auto)
CROSS_COMPILE cross-compiler toolchain prefix (default: "")
CROSS_COMPILE_<ARCH> cross-compiler toolchain prefix for
architecture "ARCH". Substitute "ARCH" for any
supported architecture (default: "")
MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
BUILD_DIR output build directory (default: ./)
BUILD_NBUILDS number of parallel targets (default: 1)
......@@ -180,13 +183,6 @@ else
JOBS=""
fi
if [ "${CROSS_COMPILE}" ] ; then
MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
else
MAKE=make
fi
if [ "${MAKEALL_LOGDIR}" ] ; then
LOG_DIR=${MAKEALL_LOGDIR}
else
......@@ -585,6 +581,18 @@ get_target_maintainers() {
echo "$mail"
}
get_target_arch() {
local target=$1
# Automatic mode
local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg`
if [ -z "${line}" ] ; then echo "" ; return ; fi
set ${line}
echo "$2"
}
list_target() {
if [ "$PRINT_MAINTS" != 'y' ] ; then
echo "$1"
......@@ -655,6 +663,16 @@ build_target() {
export BUILD_DIR="${output_dir}"
target_arch=$(get_target_arch ${target})
eval cross_toolchain=\$CROSS_COMPILE_${target_arch^^}
if [ "${cross_toolchain}" ] ; then
MAKE="make CROSS_COMPILE=${cross_toolchain}"
elif [ "${CROSS_COMPILE}" ] ; then
MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
else
MAKE=make
fi
${MAKE} distclean >/dev/null
${MAKE} -s ${target}_config
......
......@@ -22,9 +22,9 @@
#
VERSION = 2013
PATCHLEVEL = 01
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
......@@ -264,6 +264,7 @@ LIBS-y += fs/libfs.o \
fs/fdos/libfdos.o \
fs/jffs2/libjffs2.o \
fs/reiserfs/libreiserfs.o \
fs/sandbox/libsandboxfs.o \
fs/ubifs/libubifs.o \
fs/yaffs2/libyaffs2.o \
fs/zfs/libzfs.o
......
......@@ -842,7 +842,8 @@ The following options need to be configured:
CONFIG_CMD_I2C * I2C serial bus support
CONFIG_CMD_IDE * IDE harddisk support
CONFIG_CMD_IMI iminfo
CONFIG_CMD_IMLS List all found images
CONFIG_CMD_IMLS List all images found in NOR flash
CONFIG_CMD_IMLS_NAND List all images found in NAND flash
CONFIG_CMD_IMMAP * IMMR dump support
CONFIG_CMD_IMPORTENV * import an environment
CONFIG_CMD_INI * import data from an ini file into the env
......@@ -876,6 +877,7 @@ The following options need to be configured:
CONFIG_CMD_READ * Read raw data from partition
CONFIG_CMD_REGINFO * Register dump
CONFIG_CMD_RUN run command in env variable
CONFIG_CMD_SANDBOX * sb command to access sandbox features
CONFIG_CMD_SAVES * save S record dump
CONFIG_CMD_SCSI * SCSI Support
CONFIG_CMD_SDRAM * print SDRAM configuration information
......@@ -3829,6 +3831,15 @@ Low Level (hardware related) configuration options:
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
- CONFIG_ARCH_MAP_SYSMEM
Generally U-Boot (and in particular the md command) uses
effective address. It is therefore not necessary to regard
U-Boot address as virtual addresses that need to be translated
to physical addresses. However, sandbox requires this, since
it maintains its own little RAM buffer which contains all
addressable memory. This option causes some memory accesses
to be mapped through map_sysmem() / unmap_sysmem().
- CONFIG_USE_ARCH_MEMCPY
CONFIG_USE_ARCH_MEMSET
If these options are used a optimized version of memcpy/memset will
......
......@@ -104,7 +104,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
int ret;
ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
if (ret) {
if (!ret) {
/*
* There is no MAC address in the environment, so we
* initialize it from the value in the EEPROM.
......@@ -115,7 +115,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
}
if (!ret)
printf("Failed to set mac address from EEPROM\n");
printf("Failed to set mac address from EEPROM: %d\n", ret);
}
#endif /* CONFIG_DRIVER_TI_EMAC */
......
......@@ -67,7 +67,10 @@ struct davinci_gpio_bank {
#define gpio_status() gpio_info()
#define GPIO_NAME_SIZE 20
#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
#if defined(CONFIG_SOC_DM644X)
/* GPIO0 to GPIO53, omit the V3.3 volts one */
#define MAX_NUM_GPIOS 70
#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
#define MAX_NUM_GPIOS 128
#else
#define MAX_NUM_GPIOS 144
......
......@@ -286,7 +286,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
/* The malloc area is right below the monitor image in RAM */
mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
malloc_bin_reloc();
dma_alloc_init();
enable_interrupts();
......
......@@ -68,7 +68,9 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
/* Reset upon a double exception rather than just hanging.
* Do not do bfin_read on SWRST as that will reset status bits.
*/
# ifdef SWRST
bfin_write_SWRST(DOUBLE_FAULT);
# endif
#endif
serial_early_puts("Board init flash\n");
......@@ -92,7 +94,7 @@ int irq_init(void)
#elif defined(SICA_IMASK0)
bfin_write_SICA_IMASK0(0);
bfin_write_SICA_IMASK1(0);
#else
#elif defined(SIC_IMASK)
bfin_write_SIC_IMASK(0);
#endif
/* Set up a dummy NMI handler if needed. */
......
......@@ -66,6 +66,14 @@ static struct gpio_port_t * const gpio_array[] = {
(struct gpio_port_t *)PORTH_FER,
(struct gpio_port_t *)PORTI_FER,
(struct gpio_port_t *)PORTJ_FER,
#elif defined(CONFIG_BF60x)
(struct gpio_port_t *)PORTA_FER,
(struct gpio_port_t *)PORTB_FER,
(struct gpio_port_t *)PORTC_FER,
(struct gpio_port_t *)PORTD_FER,
(struct gpio_port_t *)PORTE_FER,
(struct gpio_port_t *)PORTF_FER,
(struct gpio_port_t *)PORTG_FER,
#else
# error no gpio arrays defined
#endif
......@@ -216,6 +224,12 @@ static void port_setup(unsigned gpio, unsigned short usage)
else
gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
SSYNC();
#elif defined(CONFIG_BF60x)
if (usage == GPIO_USAGE)
gpio_array[gpio_bank(gpio)]->port_fer_clear = gpio_bit(gpio);
else
gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio);
SSYNC();
#endif
}
......@@ -290,7 +304,7 @@ static void portmux_setup(unsigned short per)
}
}
}
#elif defined(CONFIG_BF54x)
#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
inline void portmux_setup(unsigned short per)
{
u32 pmux;
......@@ -330,7 +344,7 @@ inline void portmux_setup(unsigned short per)
# define portmux_setup(...) do { } while (0)
#endif
#ifndef CONFIG_BF54x
#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
/***********************************************************
*
* FUNCTIONS: Blackfin General Purpose Ports Access Functions
......@@ -534,7 +548,7 @@ int peripheral_request(unsigned short per, const char *label)
* be requested and used by several drivers
*/
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
#else
if (!(per & P_MAYSHARE)) {
......@@ -651,7 +665,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
gpio, get_label(gpio));
return -EBUSY;
}
#ifndef CONFIG_BF54x
#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
else { /* Reset POLAR setting when acquiring a gpio for the first time */
set_gpio_polar(gpio, 0);
}
......@@ -732,12 +746,16 @@ void bfin_special_gpio_free(unsigned gpio)
static inline void __bfin_gpio_direction_input(unsigned gpio)
{
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
#endif
#if defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->inen_set = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
#endif
}
int bfin_gpio_direction_input(unsigned gpio)
......@@ -785,9 +803,13 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
local_irq_save(flags);
#if defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->inen_clear = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
#endif
gpio_set_value(gpio, value);
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
......@@ -801,7 +823,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
int bfin_gpio_get_value(unsigned gpio)
{
#ifdef CONFIG_BF54x
#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
#else
unsigned long flags;
......
This diff is collapsed.
......@@ -15,6 +15,8 @@
# define serial_putc(c)
#endif
#ifndef __ADSPBF60x__
#ifndef CONFIG_EBIU_RSTCTL_VAL
# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
#endif
......@@ -30,6 +32,8 @@
# error invalid EBIU_DDRQUE value: must not set reserved bits
#endif
#endif /* __ADSPBF60x__ */
__attribute__((always_inline)) static inline void
program_async_controller(ADI_BOOT_DATA *bs)
{
......@@ -45,10 +49,13 @@ program_async_controller(ADI_BOOT_DATA *bs)
serial_putc('a');
#ifdef __ADSPBF60x__
/* Program the async banks controller. */
#ifdef EBIU_AMGCTL
bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
#endif
serial_putc('b');
......@@ -66,6 +73,51 @@ program_async_controller(ADI_BOOT_DATA *bs)
#endif
serial_putc('c');
#else /* __ADSPBF60x__ */
/* Program the static memory controller. */
# ifdef CONFIG_SMC_GCTL_VAL
bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
# endif
# ifdef CONFIG_SMC_B0CTL_VAL
bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL);
# endif
# ifdef CONFIG_SMC_B0TIM_VAL
bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL);
# endif
# ifdef CONFIG_SMC_B0ETIM_VAL
bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL);
# endif
# ifdef CONFIG_SMC_B1CTL_VAL
bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL);
# endif
# ifdef CONFIG_SMC_B1TIM_VAL
bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL);
# endif
# ifdef CONFIG_SMC_B1ETIM_VAL
bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL);
# endif
# ifdef CONFIG_SMC_B2CTL_VAL
bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL);
# endif
# ifdef CONFIG_SMC_B2TIM_VAL
bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL);
# endif
# ifdef CONFIG_SMC_B2ETIM_VAL
bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL);
# endif
# ifdef CONFIG_SMC_B3CTL_VAL
bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL);
# endif
# ifdef CONFIG_SMC_B3TIM_VAL
bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL);
# endif
# ifdef CONFIG_SMC_B3ETIM_VAL
bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
# endif
#endif
serial_putc('d');
}
#endif
......@@ -23,6 +23,7 @@
__attribute__ ((__l1_text__, __noreturn__))
static void bfin_reset(void)
{
#ifdef SWRST
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
* much as possible. This code is in L1, so it won't trigger
......@@ -66,10 +67,15 @@ static void bfin_reset(void)
: "a" (15 * 1)
: "LC1", "LB1", "LT1"
);
#endif
while (1)
#if defined(__ADSPBF60x__)
bfin_write_RCU0_CTL(0x1);
#else
/* Issue core reset */
asm("raise 1");
#endif
}
/* We need to trampoline ourselves up into L1 since our linker
......
......@@ -43,7 +43,6 @@
#include <serial.h>
#include <linux/compiler.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/uart.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -52,8 +51,8 @@ DECLARE_GLOBAL_DATA_PTR;
#include "serial.h"
#ifdef CONFIG_DEBUG_SERIAL
static uint16_t cached_lsr[256];
static uint16_t cached_rbr[256];
static uart_lsr_t cached_lsr[256];
static uart_lsr_t cached_rbr[256];
static size_t cache_count;
/* The LSR is read-to-clear on some parts, so we have to make sure status
......@@ -61,10 +60,10 @@ static size_t cache_count;
* works around anomaly 05000099 at the same time by keeping a cumulative
* tally of all the status bits.
*/
static uint16_t uart_lsr_save;
static uint16_t uart_lsr_read(uint32_t uart_base)
static uart_lsr_t uart_lsr_save;
static uart_lsr_t uart_lsr_read(uint32_t uart_base)
{
uint16_t lsr = bfin_read(&pUART->lsr);
uart_lsr_t lsr = _lsr_read(pUART);
uart_lsr_save |= (lsr & (OE|PE|FE|BI));
return lsr | uart_lsr_save;
}
......@@ -72,20 +71,20 @@ static uint16_t uart_lsr_read(uint32_t uart_base)
static void uart_lsr_clear(uint32_t uart_base)
{
uart_lsr_save = 0;
bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
_lsr_write(pUART, -1);
}
#else
/* When debugging is disabled, we only care about the DR bit, so if other
* bits get set/cleared, we don't really care since we don't read them
* anyways (and thus anomaly 05000099 is irrelevant).
*/
static inline uint16_t uart_lsr_read(uint32_t uart_base)
static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
{
return bfin_read(&pUART->lsr);
return _lsr_read(pUART);
}
static void uart_lsr_clear(uint32_t uart_base)
{
bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
_lsr_write(pUART, -1);
}
#endif
......@@ -127,20 +126,14 @@ static int uart_getc(uint32_t uart_base)
#ifdef CONFIG_DEBUG_SERIAL
/* grab & clear the LSR */
uint16_t uart_lsr_val = uart_lsr_read(uart_base);
uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
cached_lsr[cache_count] = uart_lsr_val;
cached_rbr[cache_count] = uart_rbr_val;
cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
if (uart_lsr_val & (OE|PE|FE|BI)) {
uint16_t dll, dlh;
printf("\n[SERIAL ERROR]\n");
ACCESS_LATCH();
dll = bfin_read(&pUART->dll);
dlh = bfin_read(&pUART->dlh);
ACCESS_PORT_IER();
printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
do {
--cache_count;
printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
......@@ -160,6 +153,8 @@ static int uart_getc(uint32_t uart_base)
# define LOOP(x)
#endif
#if BFIN_UART_HW_VER < 4
LOOP(
static void uart_loop(uint32_t uart_base, int state)
{
......@@ -178,6 +173,28 @@ static void uart_loop(uint32_t uart_base, int state)
}
)
#else
LOOP(
static void uart_loop(uint32_t uart_base, int state)
{
u32 control;
/* Drain the TX fifo first so bytes don't come back */
while (!(uart_lsr_read(uart_base) & TEMT))
continue;
control = bfin_read(&pUART->control);
if (state)
control |= LOOP_ENA | MRTS;
else
control &= ~(LOOP_ENA | MRTS);
bfin_write(&pUART->control, control);
}
)
#endif
#ifdef CONFIG_SYS_BFIN_UART
static void uart_puts(uint32_t uart_base, const char *s)
......@@ -246,16 +263,16 @@ struct serial_device bfin_serial##n##_device = { \
LOOP(.loop = uart##n##_loop) \
};
#ifdef UART0_DLL
#ifdef UART0_RBR
DECL_BFIN_UART(0)
#endif
#ifdef UART1_DLL
#ifdef UART1_RBR
DECL_BFIN_UART(1)
#endif
#ifdef UART2_DLL
#ifdef UART2_RBR
DECL_BFIN_UART(2)
#endif
#ifdef UART3_DLL
#ifdef UART3_RBR
DECL_BFIN_UART(3)
#endif
......@@ -274,16 +291,16 @@ __weak struct serial_device *default_serial_console(void)
void bfin_serial_initialize(void)
{
#ifdef UART0_DLL
#ifdef UART0_RBR
serial_register(&bfin_serial0_device);
#endif
#ifdef UART1_DLL
#ifdef UART1_RBR
serial_register(&bfin_serial1_device);
#endif
#ifdef UART2_DLL
#ifdef UART2_RBR
serial_register(&bfin_serial2_device);
#endif
#ifdef UART3_DLL
#ifdef UART3_RBR
serial_register(&bfin_serial3_device);
#endif
}
......@@ -293,7 +310,7 @@ void bfin_serial_initialize(void)
/* Symbol for our assembly to call. */
void serial_set_baud(uint32_t baud)
{
serial_early_set_baud(UART_DLL, baud);
serial_early_set_baud(UART_BASE, baud);
}
/* Symbol for common u-boot code to call.
......@@ -307,7 +324,7 @@ void serial_setbrg(void)
/* Symbol for our assembly to call. */
void serial_initialize(void)
{
serial_early_init(UART_DLL);
serial_early_init(UART_BASE);
}
/* Symbol for common u-boot code to call. */
......@@ -315,23 +332,23 @@ int serial_init(void)
{
serial_initialize();
serial_setbrg();
uart_lsr_clear(UART_DLL);
uart_lsr_clear(UART_BASE);
return 0;
}
int serial_tstc(void)
{
return uart_tstc(UART_DLL);
return uart_tstc(UART_BASE);
}
int serial_getc(void)
{
return uart_getc(UART_DLL);
return uart_getc(UART_BASE);
}
void serial_putc(const char c)
{
uart_putc(UART_DLL, c);
uart_putc(UART_BASE, c);
}
void serial_puts(const char *s)
......@@ -343,7 +360,7 @@ void serial_puts(const char *s)
LOOP(
void serial_loop(int state)
{
uart_loop(UART_DLL, state);
uart_loop(UART_BASE, state);
}
)
......
......@@ -3,7 +3,7 @@
* any functions defined here must be always_inline since
* initcode cannot have function calls.
*
* Copyright (c) 2004-2007 Analog Devices Inc.
* Copyright (c) 2004-2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
......@@ -12,7 +12,7 @@
#define __BFIN_CPU_SERIAL_H__
#include <asm/blackfin.h>
#include <asm/mach-common/bits/uart.h>
#include <asm/portmux.h>
#ifndef CONFIG_UART_CONSOLE
# define CONFIG_UART_CONSOLE 0
......@@ -24,88 +24,34 @@
# define BFIN_DEBUG_EARLY_SERIAL 0
#endif
#ifndef __ASSEMBLY__
#include <asm/portmux.h>
#define LOB(x) ((x) & 0xFF)
#define HIB(x) (((x) >> 8) & 0xFF)
#if defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
#if defined(__ADSPBF60x__)
# define BFIN_UART_HW_VER 4
#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
# define BFIN_UART_HW_VER 2
#else
# define BFIN_UART_HW_VER 1
#endif
/*
* All Blackfin system MMRs are padded to 32bits even if the register
* itself is only 16bits. So use a helper macro to streamline this.
*/
#define __BFP(m) u16 m; u16 __pad_##m
struct bfin_mmr_serial {
#if BFIN_UART_HW_VER == 2
__BFP(dll);
__BFP(dlh);
__BFP(gctl);
__BFP(lcr);
__BFP(mcr);
__BFP(lsr);
__BFP(msr);
__BFP(scr);
__BFP(ier_set);
__BFP(ier_clear);
__BFP(thr);
__BFP(rbr);
#else
union {
u16 dll;
u16 thr;
const u16 rbr;
};
const u16 __spad0;
union {
u16 dlh;
u16 ier;
};
const u16 __spad1;