Commit 78876704 authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init()



The DDR PHY settings no longer depend on the DRAM size.  Drop the
argument from the init function.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 4f19f611
......@@ -9,8 +9,7 @@
#include "ddrphy-regs.h"
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
bool ddr3plus)
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus)
{
u32 tmp;
......
......@@ -170,8 +170,7 @@ struct ddrphy {
#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
#ifndef __ASSEMBLY__
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
bool ddr3plus);
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus);
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
int ddrphy_training(struct ddrphy __iomem *phy);
#endif
......
......@@ -113,14 +113,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);
ddrphy_prepare_training(phy0_0, 0);
ddrphy_training(phy0_0);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);
ddrphy_prepare_training(phy1_0, 1);
ddrphy_training(phy1_0);
......
......@@ -138,32 +138,28 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size,
bd->dram_ddr3plus);
ph1_ld4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ddr3plus);
ddrphy_prepare_training(phy0_0, 0);
ddrphy_training(phy0_0);
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size,
bd->dram_ddr3plus);
ph1_ld4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ddr3plus);
ddrphy_prepare_training(phy0_1, 1);
ddrphy_training(phy0_1);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size,
bd->dram_ddr3plus);
ph1_ld4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ddr3plus);
ddrphy_prepare_training(phy1_0, 0);
ddrphy_training(phy1_0);
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size,
bd->dram_ddr3plus);
ph1_ld4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ddr3plus);
ddrphy_prepare_training(phy1_1, 1);
ddrphy_training(phy1_1);
......
......@@ -97,14 +97,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus);
ddrphy_prepare_training(phy0_0, 0);
ddrphy_training(phy0_0);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus);
ddrphy_prepare_training(phy1_0, 1);
ddrphy_training(phy1_0);
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment