Commit 799e125c authored by Jiandong Zheng's avatar Jiandong Zheng Committed by Tom Rini

arm: bcm281xx: net: Add Ethernet Driver

The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom
SoC(s) and:
- supports multiple MAC blocks,
- provides support for the Broadcom GMAC.
This driver requires MII and PHYLIB.
Signed-off-by: default avatarJiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: default avatarSteve Rae <srae@broadcom.com>
parent 2d66a0fd
...@@ -10,6 +10,8 @@ obj-$(CONFIG_ALTERA_TSE) += altera_tse.o ...@@ -10,6 +10,8 @@ obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
obj-$(CONFIG_DRIVER_AX88180) += ax88180.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
obj-$(CONFIG_BFIN_MAC) += bfin_mac.o obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_CS8900) += cs8900.o
......
This diff is collapsed.
/*
* Copyright 2014 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BCM_SF2_ETH_GMAC_H_
#define _BCM_SF2_ETH_GMAC_H_
#define BCM_SF2_ETH_MAC_NAME "gmac"
#ifndef ETHHW_PORT_INT
#define ETHHW_PORT_INT 8
#endif
#define GMAC0_REG_BASE 0x18042000
#define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE
#define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020)
#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
#define GMAC_DMA_PTR_OFFSET 0x04
#define GMAC_DMA_ADDR_LOW_OFFSET 0x08
#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
#define GMAC_DMA_STATUS0_OFFSET 0x10
#define GMAC_DMA_STATUS1_OFFSET 0x14
#define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200)
#define GMAC0_DMA_TX_PTR_ADDR \
(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
#define GMAC0_DMA_TX_ADDR_LOW_ADDR \
(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \
(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
#define GMAC0_DMA_TX_STATUS0_ADDR \
(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
#define GMAC0_DMA_TX_STATUS1_ADDR \
(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
#define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220)
#define GMAC0_DMA_RX_PTR_ADDR \
(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
#define GMAC0_DMA_RX_ADDR_LOW_ADDR \
(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \
(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
#define GMAC0_DMA_RX_STATUS0_ADDR \
(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
#define GMAC0_DMA_RX_STATUS1_ADDR \
(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
#define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808)
#define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c)
#define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810)
#define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814)
#define GMAC0_IRL_FRAMECOUNT_SHIFT 24
/* transmit channel control */
/* transmit enable */
#define D64_XC_XE 0x00000001
/* transmit suspend request */
#define D64_XC_SE 0x00000002
/* parity check disable */
#define D64_XC_PD 0x00000800
/* BurstLen bits */
#define D64_XC_BL_MASK 0x001C0000
#define D64_XC_BL_SHIFT 18
/* transmit descriptor table pointer */
/* last valid descriptor */
#define D64_XP_LD_MASK 0x00001fff
/* transmit channel status */
/* transmit state */
#define D64_XS0_XS_MASK 0xf0000000
#define D64_XS0_XS_SHIFT 28
#define D64_XS0_XS_DISABLED 0x00000000
#define D64_XS0_XS_ACTIVE 0x10000000
#define D64_XS0_XS_IDLE 0x20000000
#define D64_XS0_XS_STOPPED 0x30000000
#define D64_XS0_XS_SUSP 0x40000000
/* receive channel control */
/* receive enable */
#define D64_RC_RE 0x00000001
/* address extension bits */
#define D64_RC_AE 0x00030000
/* overflow continue */
#define D64_RC_OC 0x00000400
/* parity check disable */
#define D64_RC_PD 0x00000800
/* receive frame offset */
#define D64_RC_RO_MASK 0x000000fe
#define D64_RC_RO_SHIFT 1
/* BurstLen bits */
#define D64_RC_BL_MASK 0x001C0000
#define D64_RC_BL_SHIFT 18
/* flags for dma controller */
/* partity enable */
#define DMA_CTRL_PEN (1 << 0)
/* rx overflow continue */
#define DMA_CTRL_ROC (1 << 1)
/* receive descriptor table pointer */
/* last valid descriptor */
#define D64_RP_LD_MASK 0x00001fff
/* receive channel status */
/* current descriptor pointer */
#define D64_RS0_CD_MASK 0x00001fff
/* receive state */
#define D64_RS0_RS_MASK 0xf0000000
#define D64_RS0_RS_SHIFT 28
#define D64_RS0_RS_DISABLED 0x00000000
#define D64_RS0_RS_ACTIVE 0x10000000
#define D64_RS0_RS_IDLE 0x20000000
#define D64_RS0_RS_STOPPED 0x30000000
#define D64_RS0_RS_SUSP 0x40000000
/* descriptor control flags 1 */
/* core specific flags */
#define D64_CTRL_COREFLAGS 0x0ff00000
/* end of descriptor table */
#define D64_CTRL1_EOT ((uint32_t)1 << 28)
/* interrupt on completion */
#define D64_CTRL1_IOC ((uint32_t)1 << 29)
/* end of frame */
#define D64_CTRL1_EOF ((uint32_t)1 << 30)
/* start of frame */
#define D64_CTRL1_SOF ((uint32_t)1 << 31)
/* descriptor control flags 2 */
/* buffer byte count. real data len must <= 16KB */
#define D64_CTRL2_BC_MASK 0x00007fff
/* address extension bits */
#define D64_CTRL2_AE 0x00030000
#define D64_CTRL2_AE_SHIFT 16
/* parity bit */
#define D64_CTRL2_PARITY 0x00040000
/* control flags in the range [27:20] are core-specific and not defined here */
#define D64_CTRL_CORE_MASK 0x0ff00000
#define DC_MROR 0x00000010
#define PC_MTE 0x00800000
/* command config */
#define CC_TE 0x00000001
#define CC_RE 0x00000002
#define CC_ES_MASK 0x0000000c
#define CC_ES_SHIFT 2
#define CC_PROM 0x00000010
#define CC_PAD_EN 0x00000020
#define CC_CF 0x00000040
#define CC_PF 0x00000080
#define CC_RPI 0x00000100
#define CC_TAI 0x00000200
#define CC_HD 0x00000400
#define CC_HD_SHIFT 10
#define CC_SR 0x00002000
#define CC_ML 0x00008000
#define CC_AE 0x00400000
#define CC_CFE 0x00800000
#define CC_NLC 0x01000000
#define CC_RL 0x02000000
#define CC_RED 0x04000000
#define CC_PE 0x08000000
#define CC_TPI 0x10000000
#define CC_AT 0x20000000
#define I_PDEE 0x00000400
#define I_PDE 0x00000800
#define I_DE 0x00001000
#define I_RDU 0x00002000
#define I_RFO 0x00004000
#define I_XFU 0x00008000
#define I_RI 0x00010000
#define I_XI0 0x01000000
#define I_XI1 0x02000000
#define I_XI2 0x04000000
#define I_XI3 0x08000000
#define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU)
#define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS)
#define I_INTMASK 0x0f01fcff
#define CHIP_DRU_BASE 0x0301d000
#define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc)
#define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194)
#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0
#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13
#define AMAC0_IDM_RESET_ADDR 0x18110800
#define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408
#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6
#define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5
#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3
#define CHIPA_CHIP_ID_ADDR 0x18000000
#define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF)
#define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF)
#define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF)
#define GMAC_MII_CTRL_ADDR 0x18002000
#define GMAC_MII_CTRL_BYP_SHIFT 10
#define GMAC_MII_CTRL_EXT_SHIFT 9
#define GMAC_MII_DATA_ADDR 0x18002004
#define GMAC_MII_DATA_READ_CMD 0x60020000
#define GMAC_MII_DATA_WRITE_CMD 0x50020000
#define GMAC_MII_BUSY_SHIFT 8
#define GMAC_MII_PHY_ADDR_SHIFT 23
#define GMAC_MII_PHY_REG_SHIFT 18
#define GMAC_RESET_DELAY 2
#define HWRXOFF 30
#define MAXNAMEL 8
#define NUMTXQ 4
int gmac_add(struct eth_device *dev);
#endif /* _BCM_SF2_ETH_GMAC_H_ */
/*
* Copyright 2014 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <config.h>
#include <phy.h>
#include <miiphy.h>
#include <asm/io.h>
#include <netdev.h>
#include "bcm-sf2-eth.h"
#if defined(CONFIG_BCM_SF2_ETH_GMAC)
#include "bcm-sf2-eth-gmac.h"
#else
#error "bcm_sf2_eth: NEED to define a MAC!"
#endif
#define BCM_NET_MODULE_DESCRIPTION "Broadcom Starfighter2 Ethernet driver"
#define BCM_NET_MODULE_VERSION "0.1"
#define BCM_SF2_ETH_DEV_NAME "bcm_sf2"
static const char banner[] =
BCM_NET_MODULE_DESCRIPTION " " BCM_NET_MODULE_VERSION "\n";
static int bcm_sf2_eth_init(struct eth_device *dev)
{
struct eth_info *eth = (struct eth_info *)(dev->priv);
struct eth_dma *dma = &(eth->dma);
struct phy_device *phydev;
int rc = 0;
int i;
rc = eth->mac_init(dev);
if (rc) {
error("%s: Couldn't cofigure MAC!\n", __func__);
return rc;
}
/* disable DMA */
dma->disable_dma(dma, MAC_DMA_RX);
dma->disable_dma(dma, MAC_DMA_TX);
eth->port_num = 0;
debug("Connecting PHY 0...\n");
phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
0, dev, eth->phy_interface);
if (phydev != NULL) {
eth->port[0] = phydev;
eth->port_num += 1;
} else {
debug("No PHY found for port 0\n");
}
for (i = 0; i < eth->port_num; i++)
phy_config(eth->port[i]);
return rc;
}
/*
* u-boot net functions
*/
static int bcm_sf2_eth_send(struct eth_device *dev, void *packet, int length)
{
struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma);
uint8_t *buf = (uint8_t *)packet;
int rc = 0;
int i = 0;
debug("%s enter\n", __func__);
/* load buf and start transmit */
rc = dma->tx_packet(dma, buf, length);
if (rc) {
debug("ERROR - Tx failed\n");
return rc;
}
while (!(dma->check_tx_done(dma))) {
udelay(100);
debug(".");
i++;
if (i > 20) {
error("%s: Tx timeout: retried 20 times\n", __func__);
rc = -1;
break;
}
}
debug("%s exit rc(0x%x)\n", __func__, rc);
return rc;
}
static int bcm_sf2_eth_receive(struct eth_device *dev)
{
struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma);
uint8_t *buf = (uint8_t *)NetRxPackets[0];
int rcvlen;
int rc = 0;
int i = 0;
while (1) {
/* Poll Rx queue to get a packet */
rcvlen = dma->check_rx_done(dma, buf);
if (rcvlen < 0) {
/* No packet received */
rc = -1;
debug("\nNO More Rx\n");
break;
} else if ((rcvlen == 0) || (rcvlen > RX_BUF_SIZE)) {
error("%s: Wrong Ethernet packet size (%d B), skip!\n",
__func__, rcvlen);
break;
} else {
debug("recieved\n");
/* Forward received packet to uboot network handler */
NetReceive(buf, rcvlen);
if (++i >= PKTBUFSRX)
i = 0;
buf = NetRxPackets[i];
}
}
return rc;
}
static int bcm_sf2_eth_write_hwaddr(struct eth_device *dev)
{
struct eth_info *eth = (struct eth_info *)(dev->priv);
printf(" ETH MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->enetaddr[0], dev->enetaddr[1], dev->enetaddr[2],
dev->enetaddr[3], dev->enetaddr[4], dev->enetaddr[5]);
return eth->set_mac_addr(dev->enetaddr);
}
static int bcm_sf2_eth_open(struct eth_device *dev, bd_t *bt)
{
struct eth_info *eth = (struct eth_info *)(dev->priv);
struct eth_dma *dma = &(eth->dma);
int i;
debug("Enabling BCM SF2 Ethernet.\n");
/* Set MAC address from env */
if (bcm_sf2_eth_write_hwaddr(dev) != 0) {
error("%s: MAC set error when opening !\n", __func__);
return -1;
}
eth->enable_mac();
/* enable tx and rx DMA */
dma->enable_dma(dma, MAC_DMA_RX);
dma->enable_dma(dma, MAC_DMA_TX);
/*
* Need to start PHY here because link speed can change
* before each ethernet operation
*/
for (i = 0; i < eth->port_num; i++) {
if (phy_startup(eth->port[i])) {
error("%s: PHY %d startup failed!\n", __func__, i);
if (i == CONFIG_BCM_SF2_ETH_DEFAULT_PORT) {
error("%s: No default port %d!\n", __func__, i);
return -1;
}
}
}
/* Set MAC speed using default port */
i = CONFIG_BCM_SF2_ETH_DEFAULT_PORT;
debug("PHY %d: speed:%d, duplex:%d, link:%d\n", i,
eth->port[i]->speed, eth->port[i]->duplex, eth->port[i]->link);
eth->set_mac_speed(eth->port[i]->speed, eth->port[i]->duplex);
debug("Enable Ethernet Done.\n");
return 0;
}
static void bcm_sf2_eth_close(struct eth_device *dev)
{
struct eth_info *eth = (struct eth_info *)(dev->priv);
struct eth_dma *dma = &(eth->dma);
/* disable DMA */
dma->disable_dma(dma, MAC_DMA_RX);
dma->disable_dma(dma, MAC_DMA_TX);
eth->disable_mac();
}
int bcm_sf2_eth_register(bd_t *bis, u8 dev_num)
{
struct eth_device *dev;
struct eth_info *eth;
int rc;
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (dev == NULL) {
error("%s: Not enough memory!\n", __func__);
return -1;
}
eth = (struct eth_info *)malloc(sizeof(struct eth_info));
if (eth == NULL) {
error("%s: Not enough memory!\n", __func__);
return -1;
}
printf(banner);
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "%s_%s-%hu", BCM_SF2_ETH_DEV_NAME,
BCM_SF2_ETH_MAC_NAME, dev_num);
dev->priv = (void *)eth;
dev->iobase = 0;
dev->init = bcm_sf2_eth_open;
dev->halt = bcm_sf2_eth_close;
dev->send = bcm_sf2_eth_send;
dev->recv = bcm_sf2_eth_receive;
dev->write_hwaddr = bcm_sf2_eth_write_hwaddr;
#ifdef CONFIG_BCM_SF2_ETH_GMAC
if (gmac_add(dev)) {
free(eth);
free(dev);
error("%s: Adding GMAC failed!\n", __func__);
return -1;
}
#else
#error "bcm_sf2_eth: NEED to register a MAC!"
#endif
eth_register(dev);
#ifdef CONFIG_CMD_MII
miiphy_register(dev->name, eth->miiphy_read, eth->miiphy_write);
#endif
/* Initialization */
debug("Ethernet initialization ...");
rc = bcm_sf2_eth_init(dev);
if (rc != 0) {
error("%s: configuration failed!\n", __func__);
return -1;
}
printf("Basic ethernet functionality initialized\n");
return 0;
}
/*
* Copyright 2014 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BCM_SF2_ETH_H_
#define _BCM_SF2_ETH_H_
#include <phy.h>
#define RX_BUF_SIZE 2048
/* RX_BUF_NUM must be power of 2 */
#define RX_BUF_NUM 32
#define TX_BUF_SIZE 2048
/* TX_BUF_NUM must be power of 2 */
#define TX_BUF_NUM 2
/* Support 2 Ethernet ports now */
#define BCM_ETH_MAX_PORT_NUM 2
#define CONFIG_BCM_SF2_ETH_DEFAULT_PORT 0
enum {
MAC_DMA_TX = 1,
MAC_DMA_RX = 2
};
struct eth_dma {
void *tx_desc_aligned;
void *rx_desc_aligned;
void *tx_desc;
void *rx_desc;
uint8_t *tx_buf;
uint8_t *rx_buf;
int cur_tx_index;
int cur_rx_index;
int (*tx_packet)(struct eth_dma *dma, void *packet, int length);
bool (*check_tx_done)(struct eth_dma *dma);
int (*check_rx_done)(struct eth_dma *dma, uint8_t *buf);
int (*enable_dma)(struct eth_dma *dma, int dir);
int (*disable_dma)(struct eth_dma *dma, int dir);
};
struct eth_info {
struct eth_dma dma;
phy_interface_t phy_interface;
struct phy_device *port[BCM_ETH_MAX_PORT_NUM];
int port_num;
int (*miiphy_read)(const char *devname, unsigned char phyaddr,
unsigned char reg, unsigned short *value);
int (*miiphy_write)(const char *devname, unsigned char phyaddr,
unsigned char reg, unsigned short value);
int (*mac_init)(struct eth_device *dev);
int (*enable_mac)(void);
int (*disable_mac)(void);
int (*set_mac_addr)(unsigned char *mac);
int (*set_mac_speed)(int speed, int duplex);
};
#endif /* _BCM_SF2_ETH_H_ */
...@@ -31,6 +31,7 @@ int altera_tse_initialize(u8 dev_num, int mac_base, ...@@ -31,6 +31,7 @@ int altera_tse_initialize(u8 dev_num, int mac_base,
int at91emac_register(bd_t *bis, unsigned long iobase); int at91emac_register(bd_t *bis, unsigned long iobase);
int au1x00_enet_initialize(bd_t*); int au1x00_enet_initialize(bd_t*);
int ax88180_initialize(bd_t *bis); int ax88180_initialize(bd_t *bis);
int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
int bfin_EMAC_initialize(bd_t *bis); int bfin_EMAC_initialize(bd_t *bis);
int calxedaxgmac_initialize(u32 id, ulong base_addr); int calxedaxgmac_initialize(u32 id, ulong base_addr);
int cs8900_initialize(u8 dev_num, int base_addr); int cs8900_initialize(u8 dev_num, int base_addr);
......
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