Commit 7aaa5a60 authored by Tom Warren's avatar Tom Warren
Browse files

ARM: Tegra210: Add support to common Tegra source/config files



Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.
Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 6c43f6c8
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra210";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
gic: interrupt-controller@0,50041000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x50041000 0x0 0x1000>,
<0x0 0x50042000 0x0 0x2000>,
<0x0 0x50044000 0x0 0x2000>,
<0x0 0x50046000 0x0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
tegra_car: clock@0,60006000 {
compatible = "nvidia,tegra210-car";
reg = <0x0 0x60006000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
gpio: gpio@0,6000d000 {
compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
reg = <0x0 0x6000d000 0x0 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
i2c@0,7000c000 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>;
status = "disabled";
};
i2c@0,7000c400 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <0 84 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>;
status = "disabled";
};
i2c@0,7000c500 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <0 92 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>;
status = "disabled";
};
i2c@0,7000c700 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <0 120 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>;
status = "disabled";
};
i2c@0,7000d000 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
status = "disabled";
};
i2c@0,7000d100 {
compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
status = "disabled";
};
uarta: serial@0,70006000 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006000 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTA>;
resets = <&tegra_car 6>;
reset-names = "serial";
status = "disabled";
};
uartb: serial@0,70006040 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006040 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTB>;
resets = <&tegra_car 7>;
reset-names = "serial";
status = "disabled";
};
uartc: serial@0,70006200 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006200 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTC>;
resets = <&tegra_car 55>;
reset-names = "serial";
status = "disabled";
};
uartd: serial@0,70006300 {
compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006300 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_UARTD>;
resets = <&tegra_car 65>;
reset-names = "serial";
status = "disabled";
};
spi@0,7000d400 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d400 0x0 0x200>;
interrupts = <0 59 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC1>;
resets = <&tegra_car 41>;
reset-names = "spi";
status = "disabled";
};
spi@0,7000d600 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d600 0x0 0x200>;
interrupts = <0 82 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC2>;
resets = <&tegra_car 44>;
reset-names = "spi";
status = "disabled";
};
spi@0,7000d800 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000d800 0x0 0x200>;
interrupts = <0 83 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC3>;
resets = <&tegra_car 46>;
reset-names = "spi";
status = "disabled";
};
spi@0,7000da00 {
compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
reg = <0x0 0x7000da00 0x0 0x200>;
interrupts = <0 93 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA210_CLK_SBC4>;
resets = <&tegra_car 68>;
reset-names = "spi";
status = "disabled";
};
spi@0,70410000 {
compatible = "nvidia,tegra210-qspi";
reg = <0x0 0x70410000 0x0 0x1000>;
interrupts = <0 10 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 211>;
status = "disabled";
};
padctl: padctl@0,7009f000 {
compatible = "nvidia,tegra210-xusb-padctl";
reg = <0x0 0x7009f000 0x0 0x1000>;
resets = <&tegra_car 142>;
reset-names = "padctl";
#phy-cells = <1>;
};
sdhci@0,700b0000 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@0,700b0200 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@0,700b0400 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disabled";
};
sdhci@0,700b0600 {
compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disabled";
};
usb@0,7d000000 {
compatible = "nvidia,tegra210-ehci";
reg = <0x0 0x7d000000 0x0 0x4000>;
interrupts = <0 20 0x04>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA210_CLK_USBD>;
resets = <&tegra_car 22>;
reset-names = "usb";
status = "disabled";
};
usb@0,7d004000 {
compatible = "nvidia,tegra210-ehci";
reg = <0x0 0x7d004000 0x0 0x4000>;
interrupts = < 53 >;
phy_type = "utmi";
clocks = <&tegra_car TEGRA210_CLK_USB2>;
resets = <&tegra_car 58>;
reset-names = "usb";
status = "disabled";
};
};
/*
* (C) Copyright 2010-2011
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
......@@ -24,8 +24,6 @@
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
#define PG_UP_TAG_0 0x0
#define CORESIGHT_UNLOCK 0xC5ACCE55;
/* AP base physical address of internal SRAM */
#define NV_PA_BASE_SRAM 0x40000000
......@@ -66,7 +64,7 @@ int tegra_get_sku_info(void);
/* Do any chip-specific cache config */
void config_cache(void);
#if defined(CONFIG_TEGRA124)
#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
/* Do chip-specific vpr config */
void config_vpr(void);
#else
......
......@@ -48,6 +48,7 @@ enum {
TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
......@@ -94,7 +95,15 @@ struct clk_rst_ctlr {
uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */
uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
......@@ -136,7 +145,7 @@ struct clk_rst_ctlr {
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
/* Additional (T114) registers */
/* Additional (T114+) registers */
uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
......@@ -207,9 +216,18 @@ struct clk_rst_ctlr {
u32 _rsv32_1[7]; /* 0x574-58c */
struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
u32 _rsrv32_2[25];
/* Tegra124 */
uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
/* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
/* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
/*
* NOTE: PLLA1 regs are in the middle of this Y region. Break this in
* two later if PLLA1 is needed, but for now this is cleaner.
*/
uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
......@@ -233,6 +251,8 @@ struct clk_rst_ctlr {
#define PLL_DIVP_SHIFT 20
#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
/* Special case for T210 PLLU DIVP */
#define PLLU_DIVP_SHIFT 16
#define PLL_DIVN_SHIFT 8
#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT)
......@@ -261,6 +281,12 @@ struct clk_rst_ctlr {
#define PLL_LFCON_SHIFT 4
#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT)
/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */
#define PLLU_KVCO_SHIFT 24
#define PLLU_KVCO_MASK (3U << PLLU_KVCO_SHIFT)
#define PLLU_KCP_SHIFT 25
#define PLLU_KCP_MASK (1U << PLLU_KCP_SHIFT)
#define PLLU_VCO_FREQ_SHIFT 20
#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
......
/*
* (C) Copyright 2010-2012
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
......@@ -21,5 +21,6 @@
#define CHIPID_TEGRA30 0x30
#define CHIPID_TEGRA114 0x35
#define CHIPID_TEGRA124 0x40
#define CHIPID_TEGRA210 0x21
#endif /* _TEGRA_GP_PADCTRL_H_ */
/*
* (C) Copyright 2010,2011,2014
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
......@@ -294,6 +294,7 @@ struct pmc_ctlr {
#define CRAIL 0
#define CE0 14
#define C0NC 15
#define SOR 17
#define PMC_XOFS_SHIFT 1
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
......@@ -303,7 +304,7 @@ struct pmc_ctlr {
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 2
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
#elif defined(CONFIG_TEGRA124)
#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define TIMER_MULT_SHIFT 0
#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
#define TIMER_MULT_CPU_SHIFT 3
......@@ -314,7 +315,7 @@ struct pmc_ctlr {
#define MULT_2 1
#define MULT_4 2
#define MULT_8 3
#if defined(CONFIG_TEGRA124)
#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
#define MULT_16 4
#endif
......
/*
* (C) Copyright 2010,2011
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
......@@ -74,6 +74,7 @@ enum {
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */
SKU_ID_T210_ENG = 0x00, /* unfused value TBD */
};
/*
......@@ -88,6 +89,7 @@ enum {
TEGRA_SOC_T30,
TEGRA_SOC_T114,
TEGRA_SOC_T124,
TEGRA_SOC_T210,
TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,
......
......@@ -266,6 +266,9 @@ struct usb_ctlr {
/* USBx_UTMIP_BIAS_CFG1_0 */
#define UTMIP_FORCE_PDTRK_POWERDOWN 1
#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8
#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \
(0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
#define UTMIP_BIAS_PDTRK_COUNT_MASK \
(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
......
......@@ -34,6 +34,17 @@ config TEGRA124
bool "Tegra124 family"
select TEGRA_ARMV7_COMMON
config TEGRA210
bool "Tegra210 family"
select OF_CONTROL
select ARM64
select DM
select DM_SPI_FLASH
select DM_SERIAL
select DM_I2C
select DM_SPI
select DM_GPIO
endchoice
config SYS_MALLOC_F_LEN
......@@ -43,5 +54,6 @@ source "arch/arm/mach-tegra/tegra20/Kconfig"
source "arch/arm/mach-tegra/tegra30/Kconfig"
source "arch/arm/mach-tegra/tegra114/Kconfig"
source "arch/arm/mach-tegra/tegra124/Kconfig"
source "arch/arm/mach-tegra/tegra210/Kconfig"
endif
#
# (C) Copyright 2010,2011 Nvidia Corporation.
# (C) Copyright 2010-2015 Nvidia Corporation.
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
......@@ -24,7 +24,9 @@ obj-y += pinmux-common.o
obj-y += powergate.o
obj-y += xusb-padctl.o
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?)
obj-$(CONFIG_TEGRA124) += vpr.o
obj-$(CONFIG_TEGRA210) += vpr.o
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
ifndef CONFIG_SPL_BUILD
......@@ -35,3 +37,4 @@ obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_TEGRA30) += tegra30/
obj-$(CONFIG_TEGRA114) += tegra114/
obj-$(CONFIG_TEGRA124) += tegra124/
obj-$(CONFIG_TEGRA210) += tegra210/
/*
* (C) Copyright 2010-2014
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
......@@ -92,6 +92,13 @@ int tegra_get_chip_sku(void)
return TEGRA_SOC_T124;
}
break;
case CHIPID_TEGRA210:
switch (sku_id) {
case SKU_ID_T210_ENG:
default:
return TEGRA_SOC_T210;
}
break;
}
/* unknown chip/sku id */
......@@ -100,6 +107,7 @@ int tegra_get_chip_sku(void)
return TEGRA_SOC_UNKNOWN;
}
#ifndef CONFIG_ARM64
static void enable_scu(void)
{
struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
......@@ -222,3 +230,4 @@ void s_init(void)
/* init vpr */
config_vpr();
}
#endif
/*
* (C) Copyright 2010-2014
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
......@@ -143,12 +143,18 @@ static int uart_configs[] = {
-1,
FUNCMUX_UART4_GMI, /* UARTD */
-1,
#else /* Tegra124 */
#elif defined(CONFIG_TEGRA124)
FUNCMUX_UART1_KBC, /* UARTA */
-1,
-1,
FUNCMUX_UART4_GPIO, /* UARTD */
-1,
#else /* Tegra210 */
FUNCMUX_UART1_UART1, /* UARTA */
-1,
-1,
FUNCMUX_UART4_UART4, /* UARTD */
-1,
#endif
};
......
......@@ -21,6 +21,7 @@
#include <asm/arch-tegra/ap.h>
#include <asm/arch/gp_padctrl.h>
#ifndef CONFIG_ARM64
void config_cache(void)
{
u32 reg = 0;
......@@ -44,3 +45,4 @@ void config_cache(void)
reg |= 2;
asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
}
#endif
/*
* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
......@@ -113,7 +113,11 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
data = readl(&pll->pll_misc);
*cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
*lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
#if defined(CONFIG_TEGRA210)
/* T210 PLLU uses KCP/KVCO instead of CPCON/LFCON */
*cpcon = (data & PLLU_KCP_MASK) >> PLLU_KCP_SHIFT;
*lfcon = (data & PLLU_KVCO_MASK) >> PLLU_KVCO_SHIFT;
#endif
return 0;
}
......@@ -132,14 +136,28 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
* - same fields are always mapped at same offsets, except DCCON
* - DCCON is always 0, doesn't conflict
* - M,N, P of PLLP values are ignored for PLLP
* NOTE: Above is no longer true with T210 - TBD: FIX THIS
*/
misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
#if defined(CONFIG_TEGRA210)
/* T210 PLLU uses KCP/KVCO instead of cpcon/lfcon */
if (clkid == CLOCK_ID_USB) {
/* preserve EN_LOCKDET, set by default */
misc_data = readl(&pll->pll_misc);
misc_data |= (cpcon << PLLU_KCP_SHIFT) |
(lfcon << PLLU_KVCO_SHIFT);
}
#endif
data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
if (clkid == CLOCK_ID_USB)
#if defined(CONFIG_TEGRA210)
data |= divp << PLLU_DIVP_SHIFT;
#else
data |= divp << PLLU_VCO_FREQ_SHIFT;
#endif
else
data |= divp << PLL_DIVP_SHIFT;
if (pll) {
......@@ -534,8 +552,15 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
/* Set cpcon to PLL_MISC */
misc_reg = readl(&pll->pll_misc);
#if !defined(CONFIG_TEGRA210)
misc_reg &= ~PLL_CPCON_MASK;
misc_reg |= cpcon << PLL_CPCON_SHIFT;
#else
/* T210 uses KCP instead, use the most common bit shift (PLLA/U/D2) */
misc_reg &= ~PLLU_KCP_MASK;
misc_reg |= cpcon << PLLU_KCP_SHIFT;
#endif
writel(misc_reg, &pll->pll_misc);