Commit 7ae8350f authored by Simon Glass's avatar Simon Glass Committed by Tom Rini

ti: armv7: Move SPL SDRAM init to the right place, drop unused CONFIG_SPL_STACK

Currently in some cases SDRAM init requires global_data to be available
and soon this will not be available prior to board_init_f().  Adjust the
code paths in these cases to be correct.  In some cases we had the SPL
stack be in DDR as we might have large stacks (due to Falcon Mode +
Environment).  In these cases switch to CONFIG_SPL_STACK_R.  In other
cases we had simply been setting CONFIG_SPL_STACK into SRAM.  In these
cases we no longer need to (CONFIG_SYS_INIT_SP_ADDR is used and is also
in SRAM) so drop those lines.
Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
Tested on Beagleboard, Beagleboard xM
Tested-by: default avatarMatt Porter <mporter@konsulko.com>
Tested on Beaglebone Black, AM43xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard
Tested-by: default avatarTom Rini <trini@konsulko.com>
Signed-off-by: default avatarTom Rini <trini@konsulko.com>
Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
parent 90594919
......@@ -275,6 +275,14 @@ static void watchdog_disable(void)
;
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
board_early_init_f();
sdram_init();
}
#endif
void s_init(void)
{
/*
......@@ -290,6 +298,7 @@ void s_init(void)
setup_clocks_for_console();
uart_soft_reset();
#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
/* TODO: This does not work, gd is not available yet */
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
......@@ -298,9 +307,5 @@ void s_init(void)
/* Enable RTC32K clock */
rtc32k_enable();
#endif
#ifdef CONFIG_SPL_BUILD
board_early_init_f();
sdram_init();
#endif
}
#endif
......@@ -128,14 +128,18 @@ void s_init(void)
do_io_settings();
#endif
prcm_init();
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
#ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f();
#endif
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
#endif
}
#endif
/*
* Routine: wait_for_command_complete
......
......@@ -240,8 +240,6 @@ void try_unlock_memory(void)
*****************************************************************************/
void s_init(void)
{
int in_sdram = is_running_in_sdram();
watchdog_init();
try_unlock_memory();
......@@ -264,10 +262,14 @@ void s_init(void)
#ifdef CONFIG_USB_EHCI_OMAP
ehci_clocks_enable();
#endif
}
if (!in_sdram)
mem_init();
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
mem_init();
}
#endif
/*
* Routine: misc_init_r
......
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y
......
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
......
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
......
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="SPI_BOOT"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
......
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SYS_EXTRA_OPTIONS="NAND,SPL_USBETH_SUPPORT"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
......
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_IGEP0033=y
CONFIG_SYS_MALLOC_F=y
......
......@@ -297,7 +297,6 @@
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -306,7 +306,6 @@
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -175,7 +175,6 @@
*
* ----------------------------------------------------------------------------
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_SPL_BSS_START_ADDR 0x80A00000
......
......@@ -365,7 +365,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
/*
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
......
......@@ -213,8 +213,6 @@
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#undef CONFIG_SPL_STACK
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
......
......@@ -259,7 +259,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -142,7 +142,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (101 * 1024)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -237,7 +237,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
......
......@@ -346,7 +346,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
/*
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
......
......@@ -171,7 +171,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -136,7 +136,6 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40400000
#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -213,10 +213,9 @@
* SPLs). We have our BSS be placed 2MiB after this, to allow for the
* default Linux kernel address of 0x80008000 to work with most sized
* kernels, in the Falcon Mode case. We have the SPL malloc pool at the
* end of the BSS area. We place our stack at 32MiB after the start of
* DRAM to allow room for all of the above.
* end of the BSS area. We suggest that the stack be placed at 32MiB after
* the start of DRAM to allow room for all of the above (handled in Kconfig).
*/
#define CONFIG_SPL_STACK (CONFIG_SYS_SDRAM_BASE + (32 << 20))
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x80800000
#endif
......
......@@ -354,7 +354,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment