Commit 7beaf8b6 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Tom Rini

ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2

Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: default avatarTom Rini <trini@konsulko.com>
parent 8af1be76
......@@ -463,6 +463,9 @@ void enable_basic_clocks(void)
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
(*prcm)->cm_l3init_ocp2scp1_clkctrl,
(*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
(*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
#endif
#endif
0
};
......@@ -503,6 +506,19 @@ void enable_basic_clocks(void)
/* Enable 32 KHz clock for dwc3 */
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
/* Enable 960 MHz clock for dwc3 */
setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
OPTFCLKEN_REFCLK960M);
/* Enable 32 KHz clock for dwc3 */
setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
/* Enable 60 MHz clock for USB2PHY2 */
setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
#endif
#endif
/* Set the correct clock dividers for mmc */
......
......@@ -811,6 +811,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_clkmode_dpll_gmac = 0x4a0052a8,
.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
.cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
.cm_coreaon_l3init_60m_gfclk_clkctrl = 0x4a0086c0,
/* cm1.mpu */
.cm_mpu_mpu_clkctrl = 0x4a005320,
......@@ -921,6 +922,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
.cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0,
.cm_l3init_usb_otg_ss2_clkctrl = 0x4a009340,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009700,
......
......@@ -172,6 +172,9 @@
/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */
#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK (1 << 8)
/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0)
#define OPTFCLKEN_REFCLK960M (1 << 8)
......
......@@ -145,6 +145,7 @@ struct prcm_regs {
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */
u32 cm_coreaon_bandgap_clkctrl;
......@@ -231,6 +232,7 @@ struct prcm_regs {
u32 cm_l3init_ocp2scp1_clkctrl;
u32 cm_l3init_ocp2scp3_clkctrl;
u32 cm_l3init_usb_otg_ss1_clkctrl;
u32 cm_l3init_usb_otg_ss2_clkctrl;
u32 prm_irqstatus_mpu_2;
......
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