Commit 7d436078 authored by Prabhakar Kushwaha's avatar Prabhakar Kushwaha Committed by York Sun
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powerpc/t1040qds: Add T1040QDS board



T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.

 T1040QDS board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
    	management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
      — PCI Express: supporting Gen 1 and Gen 2;
      — SGMII
      — QSGMII
      — SATA 2.0
      — Aurora debug with dedicated connectors
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
     - NAND flash: 8-bit, async, up to 2GB.
     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
     - GASIC: Simple (minimal) target within Qixis FPGA
     - PromJET rapid memory download support
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
     - PHY #0 remains powered up during deep-sleep
 - QIXIS System Logic FPGA
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Power Supplies
 - Video
     - DIU supports video at up to 1280x1024x32bpp
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     — Two type A ports with 5V@1.5A per port.
     — Second port can be converted to OTG mini-AB
 - SDHC
     - SDHC port connects directly to an adapter card slot, featuring:
     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
     — Supporting eMMC memory devices
 - SPI
    -  On-board support of 3 different devices and sizes
 - Other IO
    - Two Serial ports
    - ProfiBus port
    - Four I2C ports
Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: default avatarYork Sun <yorksun@freescale.com>
parent 0dd38a35
......@@ -79,7 +79,9 @@ struct qixis {
u8 clk_freq[6]; /* Clock Measurement Registers */
u8 res_c6[8];
u8 clk_base[2]; /* Clock Frequency Base Reg */
u8 res_d0[16];
u8 res_d0[8];
u8 cms[2]; /* Core Management Space Address Register, 0xD8 */
u8 res_c0[6];
u8 aux2[4]; /* Auxiliary Registers,0xE0 */
u8 res14[10];
u8 aux_ad;
......
#
# Copyright 2013 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-y += law.o
COBJS-y += tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
Overview
--------
The T1040QDS is a Freescale reference board that hosts the T1040 SoC
(and variants).
T1040 SoC Overview
------------------
The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking & telecommunications.
The T1040/T1042 SoC includes the following function and features:
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
- Two RGMII interfaces or one RGMII and one MII interfaces
- High speed peripheral interfaces
- Four PCI Express 2.0 controllers running at up to 5 GHz
- Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
- Upto two QSGMII interface
- Upto six SGMII interface supporting 1000 Mbps
- One SGMII interface supporting upto 2500 Mbps
- Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
- eSPI controller
- Four I2C controllers
- Four UARTs
- Four GPIO controllers
- Integrated flash controller (IFC)
- LCD and HDMI interface (DIU) with 12 bit dual data rate
- TDM interface
- Multicore programmable interrupt controller (PIC)
- Two 8-channel DMA engines
- Single source clocking implementation
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
T1040QDS board Overview
-----------------------
- SERDES Connections, 8 lanes supporting:
— PCI Express: supporting Gen 1 and Gen 2;
— SGMII
— QSGMII
— SATA 2.0
— Aurora debug with dedicated connectors (T1040 only)
- DDR Controller
- Supports rates of up to 1600 MHz data-rate
- Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
-IFC/Local Bus
- NAND flash: 8-bit, async, up to 2GB.
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- GASIC: Simple (minimal) target within Qixis FPGA
- PromJET rapid memory download support
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep (T1040 only)
- QIXIS System Logic FPGA
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- Video
- DIU supports video at up to 1280x1024x32bpp
- USB
- Supports two USB 2.0 ports with integrated PHYs
— Two type A ports with 5V@1.5A per port.
— Second port can be converted to OTG mini-AB
- SDHC
- SDHC port connects directly to an adapter card slot, featuring:
- Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
— Supporting eMMC memory devices
- SPI
- On-board support of 3 different devices and sizes
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Memory map on T1040QDS
----------------------
The addresses in brackets are physical addresses.
Start Address End Address Description Size
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
0x0_0000_0000 0x0_ffff_ffff DDR 2GB
NOR Flash memory Map on T1040QDS
--------------------------------
Start End Definition Size
0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB
0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB
0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB
0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB
0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB
0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB
0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB
0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
Various Software configurations/environment variables/commands
--------------------------------------------------------------
The below commands apply to T1040QDS
1. U-boot environment variable hwconfig
The default hwconfig is:
hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
dr_mode=host,phy_type=utmi
Note: For USB gadget set "dr_mode=peripheral"
2. FMAN Ucode versions
fsl_fman_ucode_t1040.bin
3. Switching to alternate bank
Commands for switching to alternate bank.
1. To change from vbank0 to vbank4
=> qixis_reset altbank (it will boot using vbank4)
2.To change from vbank4 to vbank0
=> qixis reset (it will boot using vbank0)
T1040 Personality
--------------------
T1022 Personality
--------------------
T1022 is a reduced personality of T1040 with less core/clusters.
T1042 Personality
--------------------
T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
Ethernet switch. Rest of the blocks are same as T1040
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num > 2) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
pbsp = udimms[0];
/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found\n");
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
found:
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
"wrlvl_ctrl_3 0x%x\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* rtt and rtt_wr override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
return dram_size;
}
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DDR_H__
#define __DDR_H__
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
u32 cpo;
u32 write_data_delay;
u32 force_2t;
};
/*
* These tables contain all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
#endif
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
#ifndef CONFIG_SYS_NO_FLASH
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
#ifdef QIXIS_BASE_PHYS
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "../common/qixis.h"
#include "t1040qds.h"
#include "t1040qds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
char buf[64];
u8 sw;
struct cpu_type *cpu = gd->arch.cpu;
static const char *const freq[] = {"100", "125", "156.25", "161.13",
"122.88", "122.88", "122.88"};
int clock;
printf("Board: %sQDS, ", cpu->name);
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
QIXIS_READ(id), QIXIS_READ(arch));
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
if (sw < 0x8)
printf("vBank: %d\n", sw);
else if (sw == 0x8)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
printf("FPGA: v%d (%s), build %d",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
/*
* Display the actual SERDES reference clocks as configured by the
* dip switches on the board. Note that the SWx registers could
* technically be set to force the reference clocks to match the
* values that the SERDES expects (or vice versa). For now, however,
* we just display both values and hope the user notices when they
* don't match.
*/
puts("SERDES Reference: ");
sw = QIXIS_READ(brdcfg[2]);
clock = (sw >> 6) & 3;
printf("Clock1=%sMHz ", freq[clock]);
clock = (sw >> 4) & 3;
printf("Clock2=%sMHz\n", freq[clock]);
return 0;
}
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
}
return 0;
}
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_64:
return 64000000;
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
static const char *serdes_clock_to_string(u32 clock)
{
switch (clock) {
case SRDS_PLLCR0_RFCK_SEL_100:
return "100";
case SRDS_PLLCR0_RFCK_SEL_125:
return "125";
case SRDS_PLLCR0_RFCK_SEL_156_25:
return "156.25";
default:
return "Unknown frequency";
}