Commit 82d075e7 authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

ARM: uniphier: fix ROM boot mode for PH1-sLD3

Commit 4b50369f

 ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table creation requires the outer cache register
access but the page table in the sLD3 Boot ROM does not straight-map
virtual/physical addresses.

The idea here is to check the current page table to determine if
it is a straight map table.  If not, adjust the outer cache register
base.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 0efbbc5c
......@@ -99,6 +99,11 @@ ENDPROC(enable_mmu)
ENTRY(setup_init_ram)
ldr r1, = SSCO_BASE
mrc p15, 0, r0, c2, c0, 0 @ TTBR0
ldr r0, [r0, #0x400] @ entry for virtual address 0x100*****
bfc r0, #0, #20
cmp r0, #0x50000000 @ is sLD3 page table?
biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1*******
/* Touch to zero for the boot way */
0: ldr r0, = 0x00408006 @ touch to zero with address range
......
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