Commit 83ec20bc authored by TsiChungLiew's avatar TsiChungLiew Committed by John Rigby
Browse files

ColdFire: MCF52x2 update


Signed-off-by: default avatarTsiChungLiew <Tsi-Chung.Liew@freescale.com>
parent f52e7830
......@@ -27,8 +27,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START =
COBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o
START = start.o
COBJS = interrupts.o cpu.o speed.o cpu_init.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
......
......@@ -28,33 +28,15 @@
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/immap.h>
#ifdef CONFIG_M5271
#include <asm/immap_5271.h>
#include <asm/m5271.h>
#endif
#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#include <asm/m5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#include <asm/immap_5282.h>
#endif
#ifdef CONFIG_M5249
#include <asm/m5249.h>
#endif
#ifdef CONFIG_M5271
/*
* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
* determine which one we are running on, based on the Chip Identification
* Register (CIR).
*/
int checkcpu (void)
int checkcpu(void)
{
char buf[32];
unsigned short cir; /* Chip Identification Register */
......@@ -80,156 +62,164 @@ int checkcpu (void)
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
cpu_model, prn, strmhz(buf, CFG_CLK));
cpu_model, prn, strmhz(buf, CFG_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
pin, prn, strmhz(buf, CFG_CLK));
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
pin, prn, strmhz(buf, CFG_CLK));
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
mbar_writeByte(MCF_RCM_RCR,
MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
return 0;
};
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
void watchdog_reset(void)
{
mbar_writeShort(MCF_WTM_WSR, 0x5555);
mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
}
int watchdog_disable (void)
int watchdog_disable(void)
{
mbar_writeShort(MCF_WTM_WCR, 0);
return (0);
}
int watchdog_init (void)
int watchdog_init(void)
{
mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
return (0);
}
#endif /* #ifdef CONFIG_WATCHDOG */
#endif /* #ifdef CONFIG_WATCHDOG */
#endif
#ifdef CONFIG_M5272
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR);
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
wdp->wdog_wrrr = 0;
udelay (1000);
udelay(1000);
/* enable watchdog, set timeout to 0 and wait */
wdp->wdog_wrrr = 1;
while (1);
while (1) ;
/* we don't return! */
return 0;
};
int checkcpu(void) {
ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR);
int checkcpu(void)
{
volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
uchar msk;
char *suf;
char *suf;
puts ("CPU: ");
msk = (*dirp > 28) & 0xf;
puts("CPU: ");
msk = (sysctrl->sc_dir > 28) & 0xf;
switch (msk) {
case 0x2: suf = "1K75N"; break;
case 0x4: suf = "3K75N"; break;
default:
suf = NULL;
printf ("Freescale MCF5272 (Mask:%01x)\n", msk);
break;
}
case 0x2:
suf = "1K75N";
break;
case 0x4:
suf = "3K75N";
break;
default:
suf = NULL;
printf("Freescale MCF5272 (Mask:%01x)\n", msk);
break;
}
if (suf)
printf ("Freescale MCF5272 %s\n", suf);
printf("Freescale MCF5272 %s\n", suf);
return 0;
};
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset (void)
void watchdog_reset(void)
{
volatile immap_t * regp = (volatile immap_t *)CFG_MBAR;
regp->wdog_reg.wdog_wcr = 0;
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
wdt->wdog_wcr = 0;
}
int watchdog_disable (void)
int watchdog_disable(void)
{
volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */
wdt->wdog_wcr = 0; /* reset watchdog counter */
wdt->wdog_wirr = 0; /* disable watchdog interrupt */
wdt->wdog_wrrr = 0; /* disable watchdog timer */
puts ("WATCHDOG:disabled\n");
puts("WATCHDOG:disabled\n");
return (0);
}
int watchdog_init (void)
int watchdog_init(void)
{
volatile immap_t *regp = (volatile immap_t *)CFG_MBAR;
volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */
wdt->wdog_wirr = 0; /* disable watchdog interrupt */
/* set timeout and enable watchdog */
regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */
wdt->wdog_wrrr =
((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
wdt->wdog_wcr = 0; /* reset watchdog counter */
puts ("WATCHDOG:enabled\n");
puts("WATCHDOG:enabled\n");
return (0);
}
#endif /* #ifdef CONFIG_WATCHDOG */
#endif /* #ifdef CONFIG_M5272 */
#endif /* #ifdef CONFIG_WATCHDOG */
#endif /* #ifdef CONFIG_M5272 */
#ifdef CONFIG_M5282
int checkcpu (void)
int checkcpu(void)
{
unsigned char resetsource = MCFRESET_RSR;
printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
printf ("Reset:%s%s%s%s%s%s%s\n",
(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
(resetsource & MCFRESET_RSR_EXT) ? " External" : "",
(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""
);
printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
printf("Reset:%s%s%s%s%s%s%s\n",
(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
(resetsource & MCFRESET_RSR_EXT) ? " External" : "",
(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
return 0;
};
#endif
#ifdef CONFIG_M5249 /* test-only: todo... */
int checkcpu (void)
#ifdef CONFIG_M5249 /* test-only: todo... */
int checkcpu(void)
{
char buf[32];
printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK));
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
strmhz(buf, CFG_CLK));
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
/* enable watchdog, set timeout to 0 and wait */
mbar_writeByte(MCFSIM_SYPCR, 0xc0);
while (1);
while (1) ;
/* we don't return! */
return 0;
......
......@@ -27,28 +27,10 @@
#include <common.h>
#include <watchdog.h>
#ifdef CONFIG_M5271
#include <asm/m5271.h>
#include <asm/immap_5271.h>
#endif
#ifdef CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#endif
#ifdef CONFIG_M5282
#include <asm/m5282.h>
#include <asm/immap_5282.h>
#endif
#ifdef CONFIG_M5249
#include <asm/m5249.h>
#endif
#include <asm/immap.h>
#if defined(CONFIG_M5271)
void cpu_init_f (void)
void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* Disable the watchdog if we aren't using it */
......@@ -58,25 +40,35 @@ void cpu_init_f (void)
/* Set clockspeed to 100MHz */
mbar_writeShort(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK);
/* Enable UART pins */
mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
MCF_GPIO_PAR_UART_U0RXD |
MCF_GPIO_PAR_UART_U1RXD_UART1 |
MCF_GPIO_PAR_UART_U1TXD_UART1);
/* Enable Ethernet pins */
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
}
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r (void)
int cpu_init_r(void)
{
return (0);
}
void uart_port_conf(void)
{
/* Setup Ports: */
switch (CFG_UART_PORT) {
case 0:
mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
MCF_GPIO_PAR_UART_U0RXD);
break;
case 1:
mbar_writeShort(MCF_GPIO_PAR_UART,
MCF_GPIO_PAR_UART_U1RXD_UART1 |
MCF_GPIO_PAR_UART_U1TXD_UART1);
break;
case 2:
mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
break;
}
}
#endif
#if defined(CONFIG_M5272)
......@@ -87,69 +79,68 @@ int cpu_init_r (void)
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f (void)
void cpu_init_f(void)
{
/* if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
volatile immap_t *regp = (immap_t *)CFG_MBAR;
volatile unsigned char *mbar;
mbar = (volatile unsigned char *) CFG_MBAR;
volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
regp->sysctrl_reg.sc_scr = CFG_SCR;
regp->sysctrl_reg.sc_spr = CFG_SPR;
sysctrl->sc_scr = CFG_SCR;
sysctrl->sc_spr = CFG_SPR;
/* Setup Ports: */
regp->gpio_reg.gpio_pacnt = CFG_PACNT;
regp->gpio_reg.gpio_paddr = CFG_PADDR;
regp->gpio_reg.gpio_padat = CFG_PADAT;
regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;
gpio->gpio_pacnt = CFG_PACNT;
gpio->gpio_paddr = CFG_PADDR;
gpio->gpio_padat = CFG_PADAT;
gpio->gpio_pbcnt = CFG_PBCNT;
gpio->gpio_pbddr = CFG_PBDDR;
gpio->gpio_pbdat = CFG_PBDAT;
gpio->gpio_pdcnt = CFG_PDCNT;
/* Memory Controller: */
regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;
csctrl->cs_br0 = CFG_BR0_PRELIM;
csctrl->cs_or0 = CFG_OR0_PRELIM;
#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
csctrl->cs_br1 = CFG_BR1_PRELIM;
csctrl->cs_or1 = CFG_OR1_PRELIM;
#endif
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
csctrl->cs_br2 = CFG_BR2_PRELIM;
csctrl->cs_or2 = CFG_OR2_PRELIM;
#endif
#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
csctrl->cs_br3 = CFG_BR3_PRELIM;
csctrl->cs_or3 = CFG_OR3_PRELIM;
#endif
#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
csctrl->cs_br4 = CFG_BR4_PRELIM;
csctrl->cs_or4 = CFG_OR4_PRELIM;
#endif
#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
csctrl->cs_br5 = CFG_BR5_PRELIM;
csctrl->cs_or5 = CFG_OR5_PRELIM;
#endif
#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
csctrl->cs_br6 = CFG_BR6_PRELIM;
csctrl->cs_or6 = CFG_OR6_PRELIM;
#endif
#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
csctrl->cs_br7 = CFG_BR7_PRELIM;
csctrl->cs_or7 = CFG_OR7_PRELIM;
#endif
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
/* enable instruction cache now */
icache_enable();
......@@ -159,14 +150,30 @@ void cpu_init_f (void)
/*
* initialize higher level parts of CPU like timers
*/
int cpu_init_r (void)
int cpu_init_r(void)
{
return (0);
}
#endif /* #if defined(CONFIG_M5272) */
void uart_port_conf(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
switch (CFG_UART_PORT) {
case 0:
gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
break;
case 1:
gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
break;
}
}
#endif /* #if defined(CONFIG_M5272) */
#ifdef CONFIG_M5282
#if defined(CONFIG_M5282)
/*
* Breath some life into the CPU...
*
......@@ -174,7 +181,7 @@ int cpu_init_r (void)
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f (void)
void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* disable watchdog if we aren't using it */
......@@ -183,7 +190,11 @@ void cpu_init_f (void)
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
MCFCLOCK_SYNCR =
MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
/* Set up the GPIO ports */
#ifdef CFG_PEPAR
......@@ -228,29 +239,28 @@ void cpu_init_f (void)
defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
defined(CFG_CS0_WS)
MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
#if (CFG_CS0_WIDTH == 8)
#define CFG_CS0_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS0_WIDTH == 16)
#define CFG_CS0_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS0_WIDTH == 32)
#define CFG_CS0_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
#endif
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
|CFG_CS0_PS
|MCFCSM_CSCR_AA;
#if (CFG_CS0_RO != 0)
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
|MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
#else
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
#endif
MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
#if (CFG_CS0_WIDTH == 8)
#define CFG_CS0_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS0_WIDTH == 16)
#define CFG_CS0_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS0_WIDTH == 32)
#define CFG_CS0_PS MCFCSM_CSCR_PS_32
#else
#waring "Chip Select 0 are not initialized/used"
#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
#endif
MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
| CFG_CS0_PS | MCFCSM_CSCR_AA;
#if (CFG_CS0_RO != 0)
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
#endif
#else
#waring "Chip Select 0 are not initialized/used"
#endif
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
......@@ -259,29 +269,27 @@ void cpu_init_f (void)
MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
#if (CFG_CS1_WIDTH == 8)
#define CFG_CS1_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS1_WIDTH == 16)
#define CFG_CS1_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS1_WIDTH == 32)
#define CFG_CS1_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
|CFG_CS1_PS
|MCFCSM_CSCR_AA;
#if (CFG_CS1_RO != 0)
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
|MCFCSM_CSMR_WP
|MCFCSM_CSMR_V;
#else
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
|MCFCSM_CSMR_V;
#endif
#if (CFG_CS1_WIDTH == 8)
#define CFG_CS1_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS1_WIDTH == 16)
#define CFG_CS1_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS1_WIDTH == 32)
#define CFG_CS1_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
#endif
MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
| CFG_CS1_PS | MCFCSM_CSCR_AA;
#if (CFG_CS1_RO != 0)
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
| MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
| MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 1 are not initialized/used"
#warning "Chip Select 1 are not initialized/used"
#endif
#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
......@@ -290,29 +298,27 @@ void cpu_init_f (void)
MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
#if (CFG_CS2_WIDTH == 8)
#define CFG_CS2_PS MCFCSM_CSCR_PS_8
#elif (CFG_CS2_WIDTH == 16)
#define CFG_CS2_PS MCFCSM_CSCR_PS_16
#elif (CFG_CS2_WIDTH == 32)
#define CFG_CS2_PS MCFCSM_CSCR_PS_32
#else
#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
#endif
MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
|CFG_CS2_PS
|MCFCSM_CSCR_AA;
#if (CFG_CS2_RO != 0)
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
|MCFCSM_CSMR_WP
|MCFCSM_CSMR_V;
#else
MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)