Commit 84c960ce authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Add support for EmbeddedPlanet EP88x boards

Patch by Yuli Barcohen, 13 Jul 2005
parent 763b5f34
......@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4:
======================================================================
* Add support for EmbeddedPlanet EP88x boards
Patch by Yuli Barcohen, 13 Jul 2005
* Remove board specific configuration includes from the common xilinx
ethernet and iic adapter code.
Patch by Michael Libeskind, 12 Jul 2005
......
......@@ -43,16 +43,16 @@ LIST_8xx=" \
CCM IP860 NETPHONE RPXlite_DW \
cogent_mpc8xx IVML24 NETTA RRvision \
ELPT860 IVML24_128 NETTA2 SM850 \
ESTEEM192E IVML24_256 NETTA_ISDN SPD823TS \
ETX094 IVMS8 NETVIA svm_sc8xx \
FADS823 IVMS8_128 NETVIA_V2 SXNI855T \
FADS850SAR IVMS8_256 NX823 TOP860 \
FADS860T KUP4K pcu_e TQM823L \
FLAGADM KUP4X QS823 TQM823L_LCD \
FPS850L LANTEC QS850 TQM850L \
GEN860T lwmon QS860T TQM855L \
GEN860T_SC MBX quantum TQM860L \
uc100 \
EP88x IVML24_256 NETTA_ISDN SPD823TS \
ESTEEM192E IVMS8 NETVIA svm_sc8xx \
ETX094 IVMS8_128 NETVIA_V2 SXNI855T \
FADS823 IVMS8_256 NX823 TOP860 \
FADS850SAR KUP4K pcu_e TQM823L \
FADS860T KUP4X QS823 TQM823L_LCD \
FLAGADM LANTEC QS850 TQM850L \
FPS850L lwmon QS860T TQM855L \
GEN860T MBX quantum TQM860L \
GEN860T_SC uc100 \
v37 \
"
......
......@@ -441,6 +441,9 @@ cogent_mpc8xx_config: unconfig
ELPT860_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX
EP88x_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx ep88x
ESTEEM192E_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx esteem192e
......
#
# Copyright (C) 2004 Arabella Software Ltd.
# Yuli Barcohen <yuli@arabellasw.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################
#
# Copyright (C) 2005 Arabella Software Ltd.
# Yuli Barcohen <yuli@arabellasw.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Embedded Planet EP88x boards
#
TEXT_BASE = 0xFC000000
/*
* Copyright (C) 2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Support for Embedded Planet EP88x boards.
* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
/*
* SDRAM uses two Micron chips.
* Minimal CPU frequency is 40MHz.
*/
static uint sdram_table[] = {
/* Single read (offset 0x00 in UPM RAM) */
0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
/* Burst read (offset 0x08 in UPM RAM) */
0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
/* Single write (offset 0x18 in UPM RAM) */
0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
/* Burst write (offset 0x20 in UPM RAM) */
0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
/* Refresh (offset 0x30 in UPM RAM) */
0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
/* Exception (offset 0x3C in UPM RAM) */
0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05
};
int board_early_init_f (void)
{
vu_char *bcsr = (vu_char *)CFG_BCSR;
bcsr[0] |= 0x0C; /* Turn the LEDs off */
bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
flash detection by CFI driver
*/
#if defined(CONFIG_8xx_CONS_SMC1)
bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
#endif
#if defined(CONFIG_8xx_CONS_SCC2)
bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
#endif
#ifdef CONFIG_ETHER_ON_FEC1
bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
#endif
#ifdef CONFIG_ETHER_ON_FEC2
bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
#endif
return 0;
}
long int initdram (int board_type)
{
long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
/* Configure SDRAM refresh */
memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */
udelay(100);
/* Run MRS pattern from location 0x36 */
memctl->memc_mar = 0x88;
memctl->memc_mcr = 0x80002236;
udelay(100);
memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
memctl->memc_or1 |= ~(msize - 1);
return msize;
}
int checkboard( void )
{
vu_char *bcsr = (vu_char *)CFG_BCSR;
puts("Board: ");
switch (bcsr[15]) {
case 0xE7:
puts("EP88xC 1.0");
break;
default:
printf("unknown ID=%02X", bcsr[15]);
}
printf(" CPLD revision %d\n", bcsr[14]);
return 0;
}
/*
* (C) Copyright 2001-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Modified by Yuli Barcohen <yuli@arabellasw.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc8xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
ENTRY(_start)
/*
* Copyright (C) 2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* Support for Embedded Planet EP88x boards.
* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MPC885
#define CONFIG_EP88X /* Embedded Planet EP88x board */
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 38400
#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */
#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */
#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
#define CFG_DISCOVER_PHY
#define FEC_ENET
#endif /* CONFIG_FEC_ENET */
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 100000000
#define CFG_8xx_CPUCLK_MIN 40000000
#define CFG_8xx_CPUCLK_MAX 133000000
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_DHCP \
| CFG_CMD_IMMAP \
| CFG_CMD_MII \
| CFG_CMD_PING \
)
/* This must be included AFTER the definition of CONFIG_COMMANDS */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*/
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* #undef to save memory */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* Max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x400000 /* Default load address */
#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* RAM configuration (note that CFG_SDRAM_BASE must be zero)
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */
#define CFG_MAMR 0x00805000
/*
* 4096 Up to 4096 SDRAM rows
* 1000 factor s -> ms
* 32 PTP (pre-divider from MPTPR)
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
*/
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
#define CFG_RESET_ADDRESS 0x09900000
/*-----------------------------------------------------------------------
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
#else
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
#endif /* CONFIG_BZIP2 */
/*-----------------------------------------------------------------------
* Flash organisation
*/
#define CFG_FLASH_BASE 0xFC000000
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
#define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */
/* Environment is in flash */
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_OR0_PRELIM 0xFC000160
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
#define CFG_DIRECT_FLASH_TFTP
/*-----------------------------------------------------------------------
* BCSR
*/
#define CFG_OR3_PRELIM 0xFF0005B0
#define CFG_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
#define CFG_BCSR 0xFA400000
/*-----------------------------------------------------------------------
* Internal Memory Map Register
*/
#define CFG_IMMR 0xF0000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Configuration registers
*/
#ifdef CONFIG_WATCHDOG
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
SYPCR_SWF | SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
/* TBSCR - Time Base Status and Control Register */
#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
/* PISCR - Periodic Interrupt Status and Control */
#define CFG_PISCR PISCR_PS
/* SCCR - System Clock and reset Control Register */
#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR SCCR_RTSEL
#define CFG_DER 0
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
/*-----------------------------------------------------------------------
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#endif /* __CONFIG_H */
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