Commit 875e0bc6 authored by Joe Hershberger's avatar Joe Hershberger

net: mii: Fix changes made by spatch

Some of the changes were a bit too complex.
Signed-off-by: default avatarJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: default avatarBin Meng <bmeng.cn@gmail.com>
parent 5a49f174
......@@ -6,10 +6,12 @@
*/
#include <common.h>
#include <malloc.h>
#include <command.h>
#include <commproc.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
......
......@@ -264,8 +264,7 @@ int last_stage_init(void)
putc(slash[k % 8]);
}
int retval;
struct mii_dev *mdiodev = mdio_alloc();
mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN);
......
......@@ -13,6 +13,7 @@
#include <command.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mdio.h>
#include <linux/mii.h>
#include <asm/blackfin.h>
......@@ -126,6 +127,8 @@ int bfin_EMAC_initialize(bd_t *bis)
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
dev->priv = mdiodev;
#endif
return 0;
......@@ -234,8 +237,9 @@ static int bfin_EMAC_recv(struct eth_device *dev)
static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
{
const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
u16 phydat;
int phydat;
size_t count;
struct mii_dev *mdiodev = dev->priv;
/* Enable PHY output */
bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
......@@ -248,12 +252,15 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
/* turn on auto-negotiation and wait for link to come up */
bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
bfin_miiphy_write(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, MII_BMCR,
BMCR_ANENABLE);
count = 0;
while (1) {
++count;
if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
return -1;
phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR,
MDIO_DEVAD_NONE, MII_BMSR);
if (phydat < 0)
return phydat;
if (phydat & BMSR_LSTATUS)
break;
if (count > 30000) {
......@@ -264,8 +271,10 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
}
/* see what kind of link we have */
if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
return -1;
phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE,
MII_LPA);
if (phydat < 0)
return phydat;
if (phydat & LPA_DUPLEX)
*opmode = FDMODE;
else
......
......@@ -243,11 +243,10 @@ int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
if (tmp & MDIO_USERACCESS0_ACK) {
*data = tmp & 0xffff;
return(1);
return 0;
}
*data = -1;
return(0);
return -EIO;
}
/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
......@@ -268,7 +267,7 @@ int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
;
return(1);
return 0;
}
/* PHY functions for a generic PHY */
......@@ -394,7 +393,7 @@ static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
int reg)
{
unsigned short value = 0;
int retval = (davinci_eth_phy_read(addr, reg, &value) ? 0 : 1);
int retval = davinci_eth_phy_read(addr, reg, &value);
if (retval < 0)
return retval;
return value;
......@@ -403,7 +402,7 @@ static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 value)
{
return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
return davinci_eth_phy_write(addr, reg, value);
}
#endif
......
......@@ -566,7 +566,6 @@ static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad,
BUG_ON(bus->name == NULL);
BUG_ON(addr > MII_ADDRESS_MAX);
BUG_ON(reg > MII_REGISTER_MAX);
BUG_ON(&value == NULL);
/*
* Save the current SelfCTL register value. Set MAC to suppress
......
......@@ -336,25 +336,6 @@ static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad,
}
#endif
#if defined(CONFIG_PHYLIB)
int lpc32xx_eth_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
int reg_addr)
{
u16 data;
int ret;
ret = mii_reg_read(bus->name, phy_addr, reg_addr, &data);
if (ret)
return ret;
return data;
}
int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
int reg_addr, u16 data)
{
return mii_reg_write(bus->name, phy_addr, reg_addr, data);
}
#endif
/*
* Provide default Ethernet buffers base address if target did not.
* Locate buffers in SRAM at 0x00001000 to avoid cache issues and
......@@ -583,8 +564,8 @@ int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
printf("mdio_alloc failed\n");
return -ENOMEM;
}
bus->read = lpc32xx_eth_phy_read;
bus->write = lpc32xx_eth_phy_write;
bus->read = mii_reg_read;
bus->write = mii_reg_write;
strcpy(bus->name, dev->name);
ret = mdio_register(bus);
......
......@@ -230,7 +230,7 @@ static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
return retval;
return val;
}
return -1;
return -ENODEV;
}
/* wrapper for smc911x_eth_phy_write */
static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
......@@ -239,7 +239,7 @@ static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
struct eth_device *dev = eth_get_dev_by_name(bus->name);
if (dev)
return smc911x_eth_phy_write(dev, phy, reg, val);
return -1;
return -ENODEV;
}
#endif
......
......@@ -628,7 +628,7 @@ static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
unsigned short value = 0;
int devindex = 0;
if (bus->name == NULL || &value == NULL) {
if (bus->name == NULL) {
debug("%s: NULL pointer given\n", __FUNCTION__);
} else {
devindex = uec_miiphy_find_dev_by_name(bus->name);
......
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