Commit 878cd63e authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of http://git.denx.de/u-boot-samsung

parents f2ffe7da 7741c8b8
......@@ -46,11 +46,16 @@ config TARGET_SMDK5420
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_PEACH_PIT
config TARGET_PEACH_PI
bool "Peach Pi board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
config TARGET_PEACH_PIT
bool "Peach Pit board"
select SUPPORT_SPL
select OF_CONTROL if !SPL_BUILD
endchoice
config SYS_SOC
......
......@@ -118,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
else if (proid_is_exynos5250() || proid_is_exynos5420())
else if (proid_is_exynos5250() || proid_is_exynos5420()
|| proid_is_exynos5800())
div = PLL_DIV_65536;
else
return 0;
......@@ -1581,7 +1582,7 @@ static unsigned long exynos4_get_i2c_clk(void)
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
......@@ -1617,7 +1618,7 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
......@@ -1630,7 +1631,7 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_uart_clk(dev_index);
return exynos5_get_uart_clk(dev_index);
} else {
......@@ -1643,7 +1644,7 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_mmc_clk(dev_index);
return exynos5_get_mmc_clk(dev_index);
} else {
......@@ -1654,7 +1655,7 @@ unsigned long get_mmc_clk(int dev_index)
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_mmc_clk(dev_index, div);
else
exynos5_set_mmc_clk(dev_index, div);
......@@ -1668,7 +1669,7 @@ unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_lcd_clk();
else
return exynos5_get_lcd_clk();
......@@ -1682,7 +1683,7 @@ void set_lcd_clk(void)
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
else if (proid_is_exynos5420())
else if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_lcd_clk();
}
}
......@@ -1696,7 +1697,7 @@ void set_mipi_clk(void)
int set_spi_clk(int periph_id, unsigned int rate)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_set_spi_clk(periph_id, rate);
return exynos5_set_spi_clk(periph_id, rate);
} else {
......
......@@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
void system_clock_init(void)
{
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_system_clock_init();
else
exynos5250_system_clock_init();
......
......@@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
+ DMC_OFFSET);
pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
if (CONFIG_NR_DRAM_BANKS > 4) {
/* Need both controllers. */
mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
mem->chips_per_channel = 2;
mem->chips_to_configure = 2;
} else {
/* 2GB requires a single controller */
mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
}
/* Enable PAUSE for DREX */
setbits_le32(&clk->pause, ENABLE_BIT);
......@@ -832,6 +842,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
/*
* As per Exynos5800 UM ver 0.00 section 17.13.2.1
* CONCONTROL register bit 3 [update_mode], Exynos5800 does not
* support the PHY initiated update. And it is recommended to set
* this field to 1'b1 during initialization
*
* When we apply PHY-initiated mode, DLL lock value is determined
* once at DMC init time and not updated later when we change the MIF
* voltage based on ASV group in kernel. Applying MC-initiated mode
* makes sure that DLL tracing is ON so that silicon is able to
* compensate the voltage variation.
*/
val = readl(&drex0->concontrol);
val |= CONCONTROL_UPDATE_MODE;
writel(val , &drex0->concontrol);
val = readl(&drex1->concontrol);
val |= CONCONTROL_UPDATE_MODE;
writel(val , &drex1->concontrol);
return 0;
}
#endif
......@@ -837,7 +837,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_pinmux_config(peripheral, flags);
else if (proid_is_exynos5250())
return exynos5_pinmux_config(peripheral, flags);
......
......@@ -53,10 +53,37 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
}
}
void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
{
struct exynos4412_power *power =
(struct exynos4412_power *)samsung_get_base_power();
if (enable) {
/* Enabling USBHOST_PHY */
setbits_le32(&power->usbhost_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
setbits_le32(&power->hsic1_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
setbits_le32(&power->hsic2_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
} else {
/* Disabling USBHOST_PHY */
clrbits_le32(&power->usbhost_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
clrbits_le32(&power->hsic1_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
clrbits_le32(&power->hsic2_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
}
}
void set_usbhost_phy_ctrl(unsigned int enable)
{
if (cpu_is_exynos5())
exynos5_set_usbhost_phy_ctrl(enable);
else if (cpu_is_exynos4())
if (proid_is_exynos4412())
exynos4412_set_usbhost_phy_ctrl(enable);
}
static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
......
......@@ -195,10 +195,16 @@ void copy_uboot_to_ram(void)
void (*end_bootop_from_emmc)(void);
#endif
#ifdef CONFIG_USB_BOOTING
u32 (*usb_copy)(void);
int is_cr_z_set;
unsigned int sec_boot_check;
/*
* Note that older hardware (before Exynos5800) does not expect any
* arguments, but it does not hurt to pass them, so a common function
* prototype is used.
*/
u32 (*usb_copy)(u32 num_of_block, u32 *dst);
/* Read iRAM location to check for secondary USB boot mode */
sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
......@@ -240,7 +246,7 @@ void copy_uboot_to_ram(void)
*/
is_cr_z_set = config_branch_prediction(0);
usb_copy = get_irom_func(USB_INDEX);
usb_copy();
usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
config_branch_prediction(is_cr_z_set);
break;
#endif
......
......@@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb
exynos5420-peach-pit.dtb \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
......
......@@ -67,4 +67,15 @@
div = <0x3>;
index = <4>;
};
ehci@12580000 {
compatible = "samsung,exynos-ehci";
reg = <0x12580000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
phy {
compatible = "samsung,exynos-usb-phy";
reg = <0x125B0000 0x100>;
};
};
};
......@@ -131,11 +131,11 @@
};
ehci@12110000 {
samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */
samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */
samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
};
tmu@10060000 {
......
/*
* SAMSUNG/GOOGLE Peach-Pit board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "exynos54xx.dtsi"
/ {
model = "Samsung/Google Peach Pi board based on Exynos5800";
compatible = "google,pit-rev#", "google,pit",
"google,peach", "samsung,exynos5800", "samsung,exynos5";
config {
google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
hwid = "PIT TEST A-A 7848";
lazy-init = <1>;
};
aliases {
serial0 = "/serial@12C30000";
console = "/serial@12C30000";
pmic = "/i2c@12ca0000";
};
dmc {
mem-manuf = "samsung";
mem-type = "ddr3";
clock-frequency = <800000000>;
arm-frequency = <1700000000>;
};
tmu@10060000 {
samsung,min-temp = <25>;
samsung,max-temp = <125>;
samsung,start-warning = <95>;
samsung,start-tripping = <105>;
samsung,hw-tripping = <110>;
samsung,efuse-min-value = <40>;
samsung,efuse-value = <55>;
samsung,efuse-max-value = <100>;
samsung,slope = <274761730>;
samsung,dc-value = <25>;
};
/* MAX77802 is on i2c bus 4 */
i2c@12ca0000 {
clock-frequency = <400000>;
power-regulator@9 {
compatible = "maxim,max77802-pmic";
reg = <0x9>;
};
};
i2c@12cd0000 { /* i2c7 */
clock-frequency = <100000>;
soundcodec@20 {
reg = <0x20>;
compatible = "maxim,max98090-codec";
};
edp-lvds-bridge@48 {
compatible = "parade,ps8625";
reg = <0x48>;
};
};
sound@3830000 {
samsung,codec-type = "max98090";
};
i2c@12e10000 { /* i2c9 */
clock-frequency = <400000>;
tpm@20 {
compatible = "infineon,slb9645-tpm";
reg = <0x20>;
};
};
spi@12d30000 { /* spi1 */
spi-max-frequency = <50000000>;
firmware_storage_spi: flash@0 {
reg = <0>;
/*
* A region for the kernel to store a panic event
* which the firmware will add to the log.
*/
elog-panic-event-offset = <0x01e00000 0x100000>;
elog-shrink-size = <0x400>;
elog-full-threshold = <0xc00>;
};
};
spi@12d40000 { /* spi2 */
spi-max-frequency = <4000000>;
spi-deactivate-delay = <200>;
cros-ec@0 {
reg = <0>;
compatible = "google,cros-ec";
spi-half-duplex;
spi-max-timeout-ms = <1100>;
spi-frame-header = <0xec>;
ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
/*
* This describes the flash memory within the EC. Note
* that the STM32L flash erases to 0, not 0xff.
*/
#address-cells = <1>;
#size-cells = <1>;
flash@8000000 {
reg = <0x08000000 0x20000>;
erase-value = <0>;
};
};
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
};
xhci@12400000 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
};
fimd@14400000 {
samsung,vl-freq = <60>;
samsung,vl-col = <1920>;
samsung,vl-row = <1080>;
samsung,vl-width = <1920>;
samsung,vl-height = <1080>;
samsung,vl-clkp;
samsung,vl-dp;
samsung,vl-bpix = <4>;
samsung,vl-hspw = <80>;
samsung,vl-hbpd = <172>;
samsung,vl-hfpd = <60>;
samsung,vl-vspw = <10>;
samsung,vl-vbpd = <25>;
samsung,vl-vfpd = <10>;
samsung,vl-cmd-allow-len = <0xf>;
samsung,winid = <3>;
samsung,interface-mode = <1>;
samsung,dp-enabled = <1>;
samsung,dual-lcd-enabled = <0>;
};
};
......@@ -227,6 +227,13 @@ static inline void s5p_set_cpu_id(void)
/* Exynos5420 */
s5p_cpu_id = 0x5420;
break;
case 0x422:
/*
* Exynos5800 is a variant of Exynos5420
* and has product id 0x5422
*/
s5p_cpu_id = 0x5800;
break;
}
}
......@@ -255,6 +262,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210)
IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
IS_EXYNOS_TYPE(exynos5420, 0x5420)
IS_EXYNOS_TYPE(exynos5800, 0x5800)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int __attribute__((no_instrument_function)) \
......@@ -265,7 +273,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
} else if (cpu_is_exynos5()) { \
if (proid_is_exynos5420()) \
if (proid_is_exynos5420() || proid_is_exynos5800()) \
return EXYNOS5420_##base; \
return EXYNOS5_##base; \
} \
......
......@@ -450,6 +450,7 @@ enum mem_manuf {
#define CONCONTROL_RD_FETCH_SHIFT 12
#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
#define CONCONTROL_AREF_EN_SHIFT 5
#define CONCONTROL_UPDATE_MODE (1 << 3)
/* PRECHCONFIG register field */
#define PRECHCONFIG_TP_CNT_SHIFT 24
......
......@@ -12,6 +12,13 @@
#define CLK_24MHZ 5
#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0)
#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
#define RSTCON_HOSTPHY_SWRST (0xf << 3)
#define RSTCON_SWRST (0x1 << 0)
#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
#define HOST_CTRL0_COMMONON_N (1 << 9)
#define HOST_CTRL0_SIDDQ (1 << 6)
......@@ -61,6 +68,12 @@ struct exynos_usb_phy {
unsigned int usbotgtune;
};
struct exynos4412_usb_phy {
unsigned int usbphyctrl;
unsigned int usbphyclk;
unsigned int usbphyrstcon;
};
/* Switch on the VBUS power. */
int board_usb_vbus_init(void);
......
......@@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_gpio_data;
else
return exynos5_gpio_data;
......@@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void)
static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
if (proid_is_exynos5420() || proid_is_exynos5800())
return EXYNOS5420_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;
......
......@@ -210,6 +210,13 @@ struct exynos4_power {
unsigned int gps_alive_option;
};
struct exynos4412_power {
unsigned char res1[0x0704];
unsigned int usbhost_phy_control;
unsigned int hsic1_phy_control;
unsigned int hsic2_phy_control;
};
struct exynos5_power {
unsigned int om_stat;
unsigned char res1[0x18];
......
......@@ -382,6 +382,22 @@ static void board_gpio_init(void)
gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
gpio_direction_input(EXYNOS4X12_GPIO_X31);
/* Blue LED (Odroid X2/U2/U3) */
gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
#ifdef CONFIG_CMD_USB
/* USB3503A Reference frequency */
gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
/* USB3503A Connect */
gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
/* USB3503A Reset */
gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
#endif
}
static int pmic_init_max77686(void)
......@@ -462,9 +478,39 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
.usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
.usb_flags = PHY0_SLEEP,
};
#endif
#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
int board_usb_init(int index, enum usb_init_type init)
{
#ifdef CONFIG_CMD_USB
struct pmic *p_pmic;
/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
if (gd->board_type == ODROID_TYPE_U3)
gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
else
gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
/* Disconnect, Reset, Connect */
gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
/* Power off and on BUCK8 for LAN9730 */
debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
p_pmic = pmic_get("MAX77686_PMIC");
if (p_pmic && !pmic_probe(p_pmic)) {
max77686_set_buck_voltage(p_pmic, 8, 750000);
max77686_set_buck_voltage(p_pmic, 8, 3300000);
}
#endif
debug("USB_udc_probe\n");
return s3c_udc_probe(&s5pc210_otg_data);
}
......
if TARGET_PEACH_PI
config SYS_BOARD
string
default "smdk5420"
config SYS_VENDOR
string
default "samsung"
config SYS_CONFIG_NAME
string
default "peach-pi"
endif