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Librem5
uboot-imx
Commits
8a316c9b
Commit
8a316c9b
authored
Aug 01, 2005
by
Stefan Roese
Committed by
Stefan Roese
Aug 01, 2005
Browse files
Major cleanup for AMCC PPC4xx eval boards.
Patch by Stefan Roese, 01 Aug 2005
parent
c157d8e2
Changes
53
Hide whitespace changes
Inline
Side-by-side
CHANGELOG
View file @
8a316c9b
...
...
@@ -2,6 +2,18 @@
Changes for U-Boot 1.1.3:
======================================================================
* Patch by Stefan Roese, 01 Aug 2005:
- Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
(former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
for details.
- Sycamore (PPC405GPr) eval board added (Walnut port is extended
to run on both 405GP and 405GPr eval boards).
* Patch by Steven Blakeslee, 27 Jul 2005:
- Add support for AMCC PPC440EP/GR.
- Add support for AMCC Yosemite PPC440EP eval board.
- Add support for AMCC Yellowstone PPC440GR eval board.
* Fix sysmon POST problem: check I2C error codes
This fixes a problem of displaying bogus voltages when the voltages
are so low that the I2C devices start failing while the rest of the
...
...
MAINTAINERS
View file @
8a316c9b
...
...
@@ -210,6 +210,11 @@ Keith Outwater <Keith_Outwater@mvis.com>
GEN860T MPC860T
GEN860T_SC MPC860T
Stefan Roese <sr@denx.de>
sycamore PPC4xx
walnut PPC4xx
Frank Panno <fpanno@delphintech.com>
ep8260 MPC8260
...
...
@@ -327,7 +332,6 @@ Unknown / orphaned boards:
CRAYL1 PPC4xx
ERIC PPC4xx
WALNUT405 PPC4xx
MOUSSE MPC824x
...
...
MAKEALL
View file @
8a316c9b
...
...
@@ -60,16 +60,17 @@ LIST_8xx=" \
#########################################################################
LIST_4xx
=
"
\
ADCIOP AR405 ASH405
BUBINGA405EP
\
ADCIOP AR405 ASH405
bubinga
\
CANBT CPCI405 CPCI4052 CPCI405AB
\
CPCI440 CPCIISER4 CRAYL1 csb272
\
csb472 DASA_SIM DP405 DU405
\
EBONY
ERIC EXBITGEN HUB405
\
ebony
ERIC EXBITGEN HUB405
\
JSE MIP405 MIP405T ML2
\
ml300
OCOTEA
OCRTC ORSG
\
ml300
ocotea
OCRTC ORSG
\
PCI405 PIP405 PLU405 PMC405
\
PPChameleonEVB VOH405 W7OLMC W7OLMG
\
WALNUT405 WUH405 XPEDITE1K
\
walnut WUH405 XPEDITE1K yellowstone
\
yosemite
\
"
#########################################################################
...
...
Makefile
View file @
8a316c9b
...
...
@@ -707,8 +707,11 @@ AR405_config: unconfig
ASH405_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx ash405 esd
BUBINGA405EP_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx bubinga405ep
bamboo_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx bamboo amcc
bubinga_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx bubinga amcc
CANBT_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx canbt esd
...
...
@@ -759,8 +762,8 @@ DP405_config: unconfig
DU405_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx du405 esd
EBONY
_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx ebony
ebony
_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx ebony
amcc
ERIC_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx eric
...
...
@@ -794,8 +797,8 @@ ML2_config: unconfig
ml300_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx ml300 xilinx
OCOTEA
_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx ocotea
ocotea
_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx ocotea
amcc
OCRTC_config
\
ORSG_config
:
unconfig
...
...
@@ -846,6 +849,10 @@ PPChameleonEVB_HI_33_config: unconfig
sbc405_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx sbc405
sycamore_config
:
unconfig
@
echo
"Configuring for sycamore board as subset of walnut..."
@
./mkconfig
-a
walnut ppc ppc4xx walnut amcc
VOH405_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx voh405 esd
...
...
@@ -856,8 +863,8 @@ W7OLMC_config \
W7OLMG_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx w7o
WALNUT405
_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx walnut
405
walnut
_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx walnut
amcc
WUH405_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx wuh405 esd
...
...
@@ -865,6 +872,12 @@ WUH405_config: unconfig
XPEDITE1K_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx xpedite1k
yosemite_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx yosemite amcc
yellowstone_config
:
unconfig
@
./mkconfig
$
(
@:_config
=)
ppc ppc4xx yellowstone amcc
#########################################################################
## MPC8220 Systems
#########################################################################
...
...
README
View file @
8a316c9b
...
...
@@ -295,7 +295,7 @@ The following options need to be configured:
CONFIG_FADS823 CONFIG_NETVIA CONFIG_V37
CONFIG_FADS850SAR CONFIG_NX823 CONFIG_W7OLMC
CONFIG_FADS860T CONFIG_OCRTC CONFIG_W7OLMG
CONFIG_FLAGADM CONFIG_ORSG CONFIG_WALNUT
405
CONFIG_FLAGADM CONFIG_ORSG CONFIG_WALNUT
CONFIG_FPS850L CONFIG_OXC CONFIG_ZPC1900
CONFIG_FPS860L CONFIG_ZUMA
...
...
@@ -2192,7 +2192,7 @@ configurations; the following names are supported:
FADS850SAR_config omap1610h2_config TQM850L_config
FADS860T_config omap1610inn_config TQM855L_config
FPS850L_config omap5912osk_config TQM860L_config
omap2420h4_config
WALNUT405
_config
omap2420h4_config
walnut
_config
Yukon8220_config
ZPC1900_config
...
...
@@ -3135,7 +3135,7 @@ locked as (mis-) used as memory, etc.
CFG_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value
you will find in any recent u-boot distribution in
W
alnut
405
.h should work for you. I'd set it to a value larger
w
alnut.h should work for you. I'd set it to a value larger
than your SDRAM module. If you have a 64MB SDRAM module, set
it above 400_0000. Just make sure your board has no resources
that are supposed to respond to that address! That code in
...
...
board/amcc/bamboo/Makefile
0 → 100644
View file @
8a316c9b
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include
$(TOPDIR)/config.mk
LIB
=
lib
$(BOARD)
.a
OBJS
=
$(BOARD)
.o
#OBJS += flash.o
SOBJS
=
init.o
$(LIB)
:
$(OBJS) $(SOBJS)
$(AR)
crv
$@
$(OBJS)
clean
:
rm
-f
$(SOBJS)
$(OBJS)
distclean
:
clean
rm
-f
$(LIB)
core
*
.bak .depend
#########################################################################
.depend
:
Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC)
-M
$(CFLAGS)
$(SOBJS:.o=.S)
$(OBJS:.o=.c)
>
$@
sinclude
.depend
#########################################################################
board/amcc/bamboo/bamboo.c
0 → 100644
View file @
8a316c9b
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include
<common.h>
#include
<asm/processor.h>
#include
<spd_sdram.h>
int
board_early_init_f
(
void
)
{
register
uint
reg
;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr
(
ebccfga
,
xbcfg
);
reg
=
mfdcr
(
ebccfgd
);
mtdcr
(
ebccfgd
,
reg
|
0x04000000
);
/* Set ATC */
#if 0 /* test-only */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb2ap, 0x04814500);
/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
#else
mtebc
(
pb0ap
,
0x04055200
);
/* FLASH/SRAM */
mtebc
(
pb0cr
,
0xfff18000
);
/* BAS=0xfe0 1MB r/w 8-bit */
#endif
mtebc
(
pb3ap
,
0x00000000
);
mtebc
(
pb3cr
,
0x00000000
);
mtebc
(
pb4ap
,
0x00000000
);
mtebc
(
pb4cr
,
0x00000000
);
mtebc
(
pb5ap
,
0x00000000
);
mtebc
(
pb5cr
,
0x00000000
);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr
(
uic0sr
,
0xffffffff
);
/* clear all */
mtdcr
(
uic0er
,
0x00000000
);
/* disable all */
mtdcr
(
uic0cr
,
0x00000009
);
/* ATI & UIC1 crit are critical */
mtdcr
(
uic0pr
,
0xfffffe13
);
/* per ref-board manual */
mtdcr
(
uic0tr
,
0x01c00008
);
/* per ref-board manual */
mtdcr
(
uic0vr
,
0x00000001
);
/* int31 highest, base=0x000 */
mtdcr
(
uic0sr
,
0xffffffff
);
/* clear all */
mtdcr
(
uic1sr
,
0xffffffff
);
/* clear all */
mtdcr
(
uic1er
,
0x00000000
);
/* disable all */
mtdcr
(
uic1cr
,
0x00000000
);
/* all non-critical */
mtdcr
(
uic1pr
,
0xffffe0ff
);
/* per ref-board manual */
mtdcr
(
uic1tr
,
0x00ffc000
);
/* per ref-board manual */
mtdcr
(
uic1vr
,
0x00000001
);
/* int31 highest, base=0x000 */
mtdcr
(
uic1sr
,
0xffffffff
);
/* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
/*setup Address lines for flash sizes larger than 16Meg. */
out32
(
GPIO0_OSRL
,
in32
(
GPIO0_OSRL
)
|
0x40010000
);
out32
(
GPIO0_TSRL
,
in32
(
GPIO0_TSRL
)
|
0x40010000
);
out32
(
GPIO0_ISR1L
,
in32
(
GPIO0_ISR1L
)
|
0x40000000
);
/*setup emac */
out32
(
GPIO0_TCR
,
in32
(
GPIO0_TCR
)
|
0xC080
);
out32
(
GPIO0_TSRL
,
in32
(
GPIO0_TSRL
)
|
0x40
);
out32
(
GPIO0_ISR1L
,
in32
(
GPIO0_ISR1L
)
|
0x55
);
out32
(
GPIO0_OSRH
,
in32
(
GPIO0_OSRH
)
|
0x50004000
);
out32
(
GPIO0_ISR1H
,
in32
(
GPIO0_ISR1H
)
|
0x00440000
);
/*UART1 */
out32
(
GPIO1_TCR
,
in32
(
GPIO1_TCR
)
|
0x02000000
);
out32
(
GPIO1_OSRL
,
in32
(
GPIO1_OSRL
)
|
0x00080000
);
out32
(
GPIO1_ISR2L
,
in32
(
GPIO1_ISR2L
)
|
0x00010000
);
/*setup USB 2.0 */
out32
(
GPIO1_TCR
,
in32
(
GPIO1_TCR
)
|
0xc0000000
);
out32
(
GPIO1_OSRL
,
in32
(
GPIO1_OSRL
)
|
0x50000000
);
out32
(
GPIO0_TCR
,
in32
(
GPIO0_TCR
)
|
0xf
);
out32
(
GPIO0_OSRH
,
in32
(
GPIO0_OSRH
)
|
0xaa
);
out32
(
GPIO0_ISR2H
,
in32
(
GPIO0_ISR2H
)
|
0x00000500
);
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr
(
sdr_pci0
,
reg
);
mtsdr
(
sdr_pci0
,
0x80000000
|
reg
);
/* PCI arbiter enabled */
mtsdr
(
sdr_pfc0
,
0x00003e00
);
/* Pin function */
mtsdr
(
sdr_pfc1
,
0x00048000
);
/* Pin function: UART0 has 4 pins */
#if 0 /* test-only */
/*clear tmrclk divisor */
*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
/*get rid of flash write protect */
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
#endif
return
0
;
}
int
checkboard
(
void
)
{
sys_info_t
sysinfo
;
unsigned
char
*
s
=
getenv
(
"serial#"
);
get_sys_info
(
&
sysinfo
);
printf
(
"Board: Bamboo - AMCC PPC440EP Evaluation Board"
);
if
(
s
!=
NULL
)
{
puts
(
", serial# "
);
puts
(
s
);
}
putc
(
'\n'
);
printf
(
"
\t
VCO: %lu MHz
\n
"
,
sysinfo
.
freqVCOMhz
/
1000000
);
printf
(
"
\t
CPU: %lu MHz
\n
"
,
sysinfo
.
freqProcessor
/
1000000
);
printf
(
"
\t
PLB: %lu MHz
\n
"
,
sysinfo
.
freqPLB
/
1000000
);
printf
(
"
\t
OPB: %lu MHz
\n
"
,
sysinfo
.
freqOPB
/
1000000
);
printf
(
"
\t
EPB: %lu MHz
\n
"
,
sysinfo
.
freqEPB
/
1000000
);
return
(
0
);
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
void
sdram_init
(
void
)
{
register
uint
reg
;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram
(
mem_uabba
,
0x00000000
);
/* ubba=0 (default) */
mtsdram
(
mem_slio
,
0x00000000
);
/* rdre=0 wrre=0 rarw=0 */
mtsdram
(
mem_devopt
,
0x00000000
);
/* dll=0 ds=0 (normal) */
mtsdram
(
mem_clktr
,
0x40000000
);
/* ?? */
mtsdram
(
mem_wddctr
,
0x40000000
);
/* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
mtsdram
(
mem_cfg0
,
0x00000000
);
/* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
*------------------------------------------------------------------*/
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram
(
mem_b0cr
,
0x000a4001
);
/* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram
(
mem_b1cr
,
0x080a4001
);
/* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram
(
mem_tr0
,
0x410a4012
);
/* ?? */
mtsdram
(
mem_tr1
,
0x8080080b
);
/* ?? */
mtsdram
(
mem_rtr
,
0x04080000
);
/* ?? */
mtsdram
(
mem_cfg1
,
0x00000000
);
/* Self-refresh exit, disable PM */
mtsdram
(
mem_cfg0
,
0x34000000
);
/* Disable EEC */
udelay
(
400
);
/* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram
(
mem_cfg0
,
0x84000000
);
/* Enable */
for
(;;)
{
mfsdram
(
mem_mcsts
,
reg
);
if
(
reg
&
0x80000000
)
break
;
}
}
/*************************************************************************
* long int initdram
*
************************************************************************/
long
int
initdram
(
int
board
)
{
sdram_init
();
return
CFG_SDRAM_BANKS
*
(
CFG_KBYTES_SDRAM
*
1024
);
/* return bytes */
}
#if defined(CFG_DRAM_TEST)
int
testdram
(
void
)
{
unsigned
long
*
mem
=
(
unsigned
long
*
)
0
;
const
unsigned
long
kend
=
(
1024
/
sizeof
(
unsigned
long
));
unsigned
long
k
,
n
;
mtmsr
(
0
);
for
(
k
=
0
;
k
<
CFG_KBYTES_SDRAM
;
++
k
,
mem
+=
(
1024
/
sizeof
(
unsigned
long
)))
{
if
((
k
&
1023
)
==
0
)
{
printf
(
"%3d MB
\r
"
,
k
/
1024
);
}
memset
(
mem
,
0xaaaaaaaa
,
1024
);
for
(
n
=
0
;
n
<
kend
;
++
n
)
{
if
(
mem
[
n
]
!=
0xaaaaaaaa
)
{
printf
(
"SDRAM test fails at: %08x
\n
"
,
(
uint
)
&
mem
[
n
]);
return
1
;
}
}
memset
(
mem
,
0x55555555
,
1024
);
for
(
n
=
0
;
n
<
kend
;
++
n
)
{
if
(
mem
[
n
]
!=
0x55555555
)
{
printf
(
"SDRAM test fails at: %08x
\n
"
,
(
uint
)
&
mem
[
n
]);
return
1
;
}
}
}
printf
(
"SDRAM test passes
\n
"
);
return
0
;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int
pci_pre_init
(
struct
pci_controller
*
hose
)
{
unsigned
long
strap
;
unsigned
long
addr
;
/*--------------------------------------------------------------------------+
* Bamboo is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr
(
sdr_sdstp1
,
strap
);
if
((
strap
&
SDR0_SDSTP1_PAE_MASK
)
==
0
)
{
printf
(
"PCI: SDR0_STRP1[PAE] not set.
\n
"
);
printf
(
"PCI: Configuration aborted.
\n
"
);
return
0
;
}
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr
(
sdr_amp1
,
addr
);
mtsdr
(
sdr_amp1
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
plb3_acr
);
mtdcr
(
plb3_acr
,
addr
|
0x80000000
);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr
(
sdr_amp0
,
addr
);
mtsdr
(
sdr_amp0
,
(
addr
&
0x000000FF
)
|
0x0000FF00
);
addr
=
mfdcr
(
plb4_acr
)
|
0xa0000000
;
/* Was 0x8---- */
mtdcr
(
plb4_acr
,
addr
);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr
=
(
mfdcr
(
plb0_acr
)
&
~
plb0_acr_ppm_mask
)
|
plb0_acr_ppm_fair
;
addr
=
(
addr
&
~
plb0_acr_hbu_mask
)
|
plb0_acr_hbu_enabled
;
addr
=
(
addr
&
~
plb0_acr_rdp_mask
)
|
plb0_acr_rdp_4deep
;
addr
=
(
addr
&
~
plb0_acr_wrp_mask
)
|
plb0_acr_wrp_2deep
;
mtdcr
(
plb0_acr
,
addr
);
/* Segment1 */
addr
=
(
mfdcr
(
plb1_acr
)
&
~
plb1_acr_ppm_mask
)
|
plb1_acr_ppm_fair
;
addr
=
(
addr
&
~
plb1_acr_hbu_mask
)
|
plb1_acr_hbu_enabled
;
addr
=
(
addr
&
~
plb1_acr_rdp_mask
)
|
plb1_acr_rdp_4deep
;
addr
=
(
addr
&
~
plb1_acr_wrp_mask
)
|
plb1_acr_wrp_2deep
;
mtdcr
(
plb1_acr
,
addr
);
return
1
;
}
#endif
/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void
pci_target_init
(
struct
pci_controller
*
hose
)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r
(
PCIX0_PMM0MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIX0_PMM0LA
,
CFG_PCI_MEMBASE
);
/* PMM0 Local Address */
out32r
(
PCIX0_PMM0PCILA
,
CFG_PCI_MEMBASE
);
/* PMM0 PCI Low Address */
out32r
(
PCIX0_PMM0PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIX0_PMM0MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIX0_PMM1MA
,
0x00000000
);
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r
(
PCIX0_PMM1LA
,
CFG_PCI_MEMBASE2
);
/* PMM0 Local Address */
out32r
(
PCIX0_PMM1PCILA
,
CFG_PCI_MEMBASE2
);
/* PMM0 PCI Low Address */
out32r
(
PCIX0_PMM1PCIHA
,
0x00000000
);
/* PMM0 PCI High Address */
out32r
(
PCIX0_PMM1MA
,
0xE0000001
);
/* 512M + No prefetching, and enable region */
out32r
(
PCIX0_PTM1MS
,
0x00000001
);
/* Memory Size/Attribute */
out32r
(
PCIX0_PTM1LA
,
0
);
/* Local Addr. Reg */
out32r
(
PCIX0_PTM2MS
,
0
);
/* Memory Size/Attribute */
out32r
(
PCIX0_PTM2LA
,
0
);
/* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_VENDOR_ID
,
CFG_PCI_SUBSYS_VENDORID
);
pci_write_config_word
(
0
,
PCI_SUBSYSTEM_ID
,
CFG_PCI_SUBSYS_ID
);
/* Configure command register as bus master */
pci_write_config_word
(
0
,
PCI_COMMAND
,
PCI_COMMAND_MASTER
);
/* 240nS PCI clock */
pci_write_config_word
(
0
,
PCI_LATENCY_TIMER
,
1
);
/* No error reporting */
pci_write_config_word
(
0
,
PCI_ERREN
,
0
);
pci_write_config_dword
(
0
,
PCI_BRDGOPT2
,
0x00000101
);
}
#endif
/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void
pci_master_init
(
struct
pci_controller
*
hose
)
{
unsigned
short
temp_short
;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word
(
0
,
PCI_COMMAND
,
&
temp_short
);
pci_write_config_word
(
0
,
PCI_COMMAND
,
temp_short
|
PCI_COMMAND_MASTER
|
PCI_COMMAND_MEMORY
);
}
#endif
/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int
is_pci_host
(
struct
pci_controller
*
hose
)
{