Commit 8b5ab4c1 authored by Michael Schwingen's avatar Michael Schwingen Committed by Albert ARIBAUD

update/fix AcTux3 board

Signed-off-by: default avatarMichael Schwingen <michael@schwingen.org>
parent af050485
......@@ -36,72 +36,76 @@
#include <malloc.h>
#include <asm/arch/ixp425.h>
#include <asm/io.h>
#include <miiphy.h>
#include "actux3_hw.h"
DECLARE_GLOBAL_DATA_PTR;
int board_init (void)
int board_early_init_f(void)
{
/* CS1: IPAC-X */
writel(0x94d10013, IXP425_EXP_CS1);
/* CS5: Debug port */
writel(0x9d520003, IXP425_EXP_CS5);
/* CS6: Release/Option register */
writel(0x81860001, IXP425_EXP_CS6);
/* CS7: LEDs */
writel(0x80900003, IXP425_EXP_CS7);
return 0;
}
int board_init(void)
{
gd->bd->bi_arch_number = MACH_TYPE_ACTUX3;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
/*
* Setup GPIO's for Interrupt inputs
*/
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
/*
* Setup GPIO's for 33MHz clock output
*/
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
*IXP425_GPIO_GPCLKR = 0x011001FF;
/* CS1: IPAC-X */
*IXP425_EXP_CS1 = 0x94d10013;
/* CS5: Debug port */
*IXP425_EXP_CS5 = 0x9d520003;
/* CS6: Release/Option register */
*IXP425_EXP_CS6 = 0x81860001;
/* CS7: LEDs */
*IXP425_EXP_CS7 = 0x80900003;
udelay (533);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
ACTUX3_LED1_RT (1);
ACTUX3_LED1_GN (0);
ACTUX3_LED2_RT (0);
ACTUX3_LED2_GN (0);
ACTUX3_LED3_RT (0);
ACTUX3_LED3_GN (0);
ACTUX3_LED4_GN (0);
ACTUX3_LED5_RT (0);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
writel(0x011001FF, IXP425_GPIO_GPCLKR);
/* we need a minimum PCI reset pulse width after enabling the clock */
udelay(533);
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
ACTUX3_LED1_RT(1);
ACTUX3_LED1_GN(0);
ACTUX3_LED2_RT(0);
ACTUX3_LED2_GN(0);
ACTUX3_LED3_RT(0);
ACTUX3_LED3_GN(0);
ACTUX3_LED4_GN(0);
ACTUX3_LED5_RT(0);
return 0;
}
......@@ -109,21 +113,21 @@ int board_init (void)
/*
* Check Board Identity
*/
int checkboard (void)
int checkboard(void)
{
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
puts ("Board: AcTux-3 rev.");
putc (ACTUX3_BOARDREL + 'A' - 1);
puts("Board: AcTux-3 rev.");
putc(ACTUX3_BOARDREL + 'A' - 1);
if (i > 0) {
puts (", serial# ");
puts (buf);
}
putc ('\n');
putc('\n');
return (0);
return 0;
}
/*************************************************************************
......@@ -132,34 +136,32 @@ int checkboard (void)
* 1 = Rev. A
* 2 = Rev. B
*************************************************************************/
u32 get_board_rev (void)
u32 get_board_rev(void)
{
return ACTUX3_BOARDREL;
}
int dram_init (void)
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return (0);
gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
return 0;
}
void reset_phy (void)
void reset_phy(void)
{
int i;
/* initialize the PHY */
miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
miiphy_reset("NPE0", CONFIG_PHY_ADDR);
/* all LED outputs = Link/Act */
miiphy_write ("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
/*
* The Marvell 88E6060 switch comes up with all ports disabled.
* set all ethernet switch ports to forwarding state
*/
for (i = 1; i <= 5; i++)
miiphy_write ("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
}
CONFIG_SYS_TEXT_BASE = 0x00e00000
# include NPE ethernet driver
BOARDLIBS = arch/arm/cpu/ixp/npe/libnpe.o
......@@ -30,34 +30,29 @@ SECTIONS
. = ALIGN (4);
.text : {
arch/arm/cpu/ixp/start.o (.text)
lib/string.o (.text)
lib/vsprintf.o (.text)
arch/arm/lib/board.o (.text)
common/dlmalloc.o (.text)
arch/arm/cpu/ixp/cpu.o (.text)
arch/arm/cpu/ixp/start.o(.text*)
net/libnet.o(.text*)
board/actux3/libactux3.o(.text*)
arch/arm/cpu/ixp/libixp.o(.text*)
drivers/serial/libserial.o(.text*)
. = env_offset;
common/env_embedded.o (.ppcenv)
* (.text)
common/env_embedded.o(.ppcenv)
*(.text*)
}
. = ALIGN (4);
. = ALIGN(4);
.rodata : {
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
. = ALIGN (4);
. = ALIGN(4);
.data : {
*(.data)
*(.data*)
}
. = ALIGN (4);
. = ALIGN(4);
.got : {
*(.got)
}
. =.;
__u_boot_cmd_start =.;
.u_boot_cmd : {
......@@ -66,10 +61,27 @@ SECTIONS
__u_boot_cmd_end =.;
. = ALIGN (4);
__bss_start =.;
.bss (NOLOAD): {
*(.bss)
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
}
.dynsym : {
__dynsym_start = .;
*(.dynsym)
}
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(4);
_end = .;
}
__bss_end__ =.;
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}
......@@ -37,12 +37,12 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds"
/***************************************************************
* U-boot generic defines start here.
***************************************************************/
#undef CONFIG_USE_IRQ
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
......@@ -82,8 +82,9 @@
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x00800000
/* spec says 66.666 MHz, but it appears to be 33 */
#define CONFIG_SYS_HZ 3333333
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
#define CONFIG_SYS_HZ 1000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
......@@ -99,10 +100,6 @@
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113442
......@@ -110,7 +107,7 @@
/* SDRAM settings */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
#define CONFIG_SYS_DRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* 16MB SDRAM */
#define CONFIG_SYS_SDR_CONFIG 0x3A
......@@ -120,6 +117,7 @@
#define CONFIG_SYS_DRAM_SIZE 0x01000000
/* FLASH organization */
#define CONFIG_SYS_TEXT_BASE 0x50000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 140
......@@ -129,6 +127,7 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_BOARD_SIZE_LIMIT 262144
/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
......@@ -149,6 +148,11 @@
#define CONFIG_PHY_ADDR 0x10
/* MII PHY management */
#define CONFIG_MII 1
/* fixed-speed switch without standard PHY registers on MII */
#define CONFIG_MII_NPE0_FIXEDLINK 1
#define CONFIG_MII_NPE0_SPEED 100
#define CONFIG_MII_NPE0_FULLDUPLEX 1
/* Number of ethernet rx buffers & descriptors */
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_RESET_PHY_R 1
......@@ -183,13 +187,15 @@
"npe_ucode=50040000\0" \
"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
"kerneladdr=50050000\0" \
"kernelfile=actux3/uImage\0" \
"rootfile=actux3/rootfs\0" \
"rootaddr=50170000\0" \
"loadaddr=10000\0" \
"updateboot_ser=mw.b 10000 ff 40000;" \
" loady ${loadaddr};" \
" run eraseboot writeboot\0" \
"updateboot_net=mw.b 10000 ff 40000;" \
" tftp ${loadaddr} u-boot.bin;" \
" tftp ${loadaddr} actux3/u-boot.bin;" \
" run eraseboot writeboot\0" \
"eraseboot=protect off 50000000 50003fff;" \
" protect off 50006000 5003ffff;" \
......@@ -197,8 +203,9 @@
" erase 50006000 5003ffff\0" \
"writeboot=cp.b 10000 50000000 4000;" \
" cp.b 16000 50006000 3a000\0" \
"eraseenv=protect off 50004000 50005fff;" \
" erase 50004000 50005fff\0" \
"updateucode=loady;" \
" era ${npe_ucode} +${filesize};" \
" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
"updateroot=tftp ${loadaddr} ${rootfile};" \
" era ${rootaddr} +${filesize};" \
" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
......@@ -209,7 +216,7 @@
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
"boot_flash=run flashargs addtty addeth;" \
" bootm ${kerneladdr}\0" \
......@@ -217,4 +224,8 @@
" tftpboot ${loadaddr} ${kernelfile};" \
" bootm\0"
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
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