Commit 8bd522ce authored by Dave Liu's avatar Dave Liu Committed by Kim Phillips

mpc83xx: Add the support for MPC8315ERDB board

The features list:
- Boot from NOR Flash
- DDR2 266MHz hardcoded configuration
- Local bus NOR Flash R/W operation
- I2C, UART, MII and RTC
- eTSEC0/1 support
- PCI host
Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
parent b05884ef
......@@ -305,7 +305,7 @@ W: http://www.li-pro.net
N: Dave Liu
E: daveliu@freescale.com
D: Support for MPC832x, MPC8360, MPC837x
D: Support for MPC8315, MPC832x, MPC8360, MPC837x
W: www.freescale.com
N: Raymond Lo
......
......@@ -232,6 +232,7 @@ The LEOX team <team@leox.org>
Dave Liu <daveliu@freescale.com>
MPC8315ERDB MPC8315
MPC832XEMDS MPC832x
MPC8360EMDS MPC8360
MPC837XEMDS MPC837x
......
......@@ -309,6 +309,7 @@ LIST_8260=" \
LIST_83xx=" \
MPC8313ERDB_33 \
MPC8313ERDB_66 \
MPC8315ERDB \
MPC8323ERDB \
MPC832XEMDS \
MPC832XEMDS_ATM \
......
......@@ -1861,6 +1861,9 @@ MPC8313ERDB_66_config: unconfig
fi ;
@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
MPC8315ERDB_config: unconfig
@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
MPC8323ERDB_config: unconfig
@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* Author: Scott Wood <scottwood@freescale.com>
* Dave Liu <daveliu@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <pci.h>
#include <mpc83xx.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
gd->flags |= GD_FLG_SILENT;
return 0;
}
static u8 read_board_info(void)
{
u8 val8;
i2c_set_bus_num(0);
if (i2c_read(CFG_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
return val8;
else
return 0;
}
int checkboard(void)
{
static const char * const rev_str[] = {
"0.0",
"0.1",
"1.0",
"1.1",
"<unknown>",
};
u8 info;
int i;
info = read_board_info();
i = (!info) ? 4: info & 0x03;
printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
return 0;
}
static struct pci_region pci_regions[] = {
{
bus_start: CFG_PCI_MEM_BASE,
phys_start: CFG_PCI_MEM_PHYS,
size: CFG_PCI_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CFG_PCI_MMIO_BASE,
phys_start: CFG_PCI_MMIO_PHYS,
size: CFG_PCI_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
bus_start: CFG_PCI_IO_BASE,
phys_start: CFG_PCI_IO_PHYS,
size: CFG_PCI_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
clk->occr |= 0xe0000000;
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
mpc83xx_pci_init(1, reg, warmboot);
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* Authors: Nick.Spence@freescale.com
* Wilson.Lo@freescale.com
* scottwood@freescale.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
static void resume_from_sleep(void)
{
u32 magic = *(u32 *)0;
typedef void (*func_t)(void);
func_t resume = *(func_t *)4;
if (magic == 0xf5153ae5)
resume();
gd->flags &= ~GD_FLG_SILENT;
puts("\nResume from sleep failed: bad magic word\n");
}
/* Fixed sdram init -- doesn't use serial presence detect.
*
* This is useful for faster booting in configs where the RAM is unlikely
* to be changed, or for things like NAND booting where space is tight.
*/
static long fixed_sdram(void)
{
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
/*
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
* or the DDR2 controller may fail to initialize correctly.
*/
udelay(50000);
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
/* Currently we use only one CS, so disable the other bank. */
im->ddr.cs_config[1] = 0;
im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG | SDRAM_CFG_BI;
else
im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CFG_DDR_MODE;
im->ddr.sdram_mode2 = CFG_DDR_MODE2;
im->ddr.sdram_interval = CFG_DDR_INTERVAL;
sync();
/* enable DDR controller */
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
sync();
return msize;
}
long int initdram(int board_type)
{
volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
/* DDR SDRAM */
msize = fixed_sdram();
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
resume_from_sleep();
/* return total bus SDRAM size(bytes) -- DDR */
return msize;
}
Freescale MPC8315ERDB Board
-----------------------------------------
1. Board Switches and Jumpers
S3 is used to set CFG_RESET_SOURCE.
To boot the image at 0xFE000000 in NOR flash, use these DIP
switche settings for S3 S4:
+------+ +------+
| | | **** |
| **** | | |
+------+ ON +------+ ON
4321 4321
(where the '*' indicates the position of the tab of the switch.)
2. Memory Map
The memory map looks like this:
0x0000_0000 0x07ff_ffff DDR 128M
0x8000_0000 0x8fff_ffff PCI MEM 256M
0x9000_0000 0x9fff_ffff PCI_MMIO 256M
0xe000_0000 0xe00f_ffff IMMR 1M
0xe030_0000 0xe03f_ffff PCI IO 1M
0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
3. Definitions
3.1 Explanation of NEW definitions in:
include/configs/MPC8315ERDB.h
CONFIG_MPC83xx MPC83xx family
CONFIG_MPC831x MPC831x specific
CONFIG_MPC8315 MPC8315 specific
CONFIG_MPC8315ERDB MPC8315ERDB board specific
4. Compilation
Assuming you're using BASH (or similar) as your shell:
export CROSS_COMPILE=your-cross-compiler-prefix-
make distclean
make MPC8315ERDB_config
make all
5. Downloading and Flashing Images
5.1 Reflash U-boot Image using U-boot
tftp 40000 u-boot.bin
protect off all
erase fe000000 fe1fffff
cp.b 40000 fe000000 xxxx
protect on all
You have to supply the correct byte count with 'xxxx'
from the TFTP result log.
5.2 Downloading and Booting Linux Kernel
Ensure that all networking-related environment variables are set
properly (including ipaddr, serverip, gatewayip (if needed),
netmask, ethaddr, eth1addr, rootpath (if using NFS root),
fdtfile, and bootfile).
Then, do one of the following, depending on whether you
want an NFS root or a ramdisk root:
=>run nfsboot
or
=>run ramboot
6 Notes
Booting from NAND flash is not yet supported.
The console baudrate for MPC8315ERDB is 115200bps.
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