Commit 8d949aff authored by Srikanth Srinivasan's avatar Srikanth Srinivasan Committed by Andy Fleming
Browse files

mpc85xx: Add support for the P2020



Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020
Signed-off-by: default avatarSrikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: default avatarTravis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent cb69e4de
......@@ -48,6 +48,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
# supports ddr1/2/3
COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
......
......@@ -62,6 +62,8 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8568, 8568_E),
CPU_TYPE_ENTRY(8572, 8572),
CPU_TYPE_ENTRY(8572, 8572_E),
CPU_TYPE_ENTRY(P2020, P2020),
CPU_TYPE_ENTRY(P2020, P2020_E),
};
struct cpu_type *identify_cpu(u32 ver)
......
......@@ -38,7 +38,8 @@ DECLARE_GLOBAL_DATA_PTR;
defined(CONFIG_MPC8568) || \
defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
#define FSL_HW_NUM_LAWS 10
#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572)
#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
#else
#error FSL_HW_NUM_LAWS not defined for this platform
......
......@@ -42,7 +42,7 @@ enum law_trgt_if {
#ifndef CONFIG_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
#ifndef CONFIG_MPC8572
#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
LAW_TRGT_IF_LBC = 0x04,
......@@ -61,7 +61,7 @@ enum law_trgt_if {
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
#endif
#ifdef CONFIG_MPC8572
#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
......
......@@ -58,7 +58,23 @@ typedef struct ccsr_local_ecm {
uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
char res19[4];
uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */
char res19_8a[20];
uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
char res19_8b[4];
uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
char res19_9a[20];
uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
char res19_9b[4];
uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
char res19_10a[20];
uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */
char res19_10b[4];
uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */
char res19_11a[20];
uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */
char res19_11b[4];
uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */
char res20[652];
uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
char res21[12];
uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
......@@ -119,7 +135,12 @@ typedef struct ccsr_ddr {
uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
char res8_1b[2672];
char res8_1b[2456];
uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */
uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */
uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */
uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */
char res8_1c[200];
uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
char res8_2[512];
......
......@@ -951,6 +951,8 @@
#define SVR_8568_E 0x807D00
#define SVR_8572 0x80E000
#define SVR_8572_E 0x80E800
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
......
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