Commit 8e9c897b authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Nobuhiro Iwamatsu
Browse files

sh: add support for sh7757lcr board



The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM,
Ethernet, and more.

This patch supports the following functions:
 - 256MB DDR3-SDRAM
 - SPI ROM
 - Ethernet
Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: default avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
parent 6639562e
......@@ -1025,6 +1025,7 @@ Mark Jonas <mark.jonas@de.bosch.com>
Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
MS7720SE SH7720
R0P77570030RL SH7757
R0P77850011RL SH7785
#########################################################################
......
......@@ -44,6 +44,8 @@
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h>
#elif defined (CONFIG_CPU_SH7757)
# include <asm/cpu_sh7757.h>
#elif defined (CONFIG_CPU_SH7763)
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
......
/*
* Copyright (C) 2011 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _ASM_CPU_SH7757_H_
#define _ASM_CPU_SH7757_H_
#define CCR 0xFF00001C
#define WTCNT 0xFFCC0000
#define CCR_CACHE_INIT 0x0000090b
#define CACHE_OC_NUM_WAYS 1
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
/* MMU */
struct mmu_regs {
unsigned int reserved[4];
unsigned int mmucr;
};
#define MMU_BASE ((struct mmu_regs *)0xff000000)
/* Watchdog */
#define WTCSR0 0xffcc0002
#define WRSTCSR_R 0xffcc0003
#define WRSTCSR_W 0xffcc0002
#define WTCSR_PREFIX 0xa500
#define WRSTCSR_PREFIX 0x6900
#define WRSTCSR_WOVF_PREFIX 0x9600
/* SCIF */
#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
/* SerMux */
#define SMR0 0xfe470000
/* TMU0 */
#define TSTR 0xFE430004
#define TOCR 0xFE430000
#define TSTR0 0xFE430004
#define TCOR0 0xFE430008
#define TCNT0 0xFE43000C
#define TCR0 0xFE430010
#define TCOR1 0xFE430014
#define TCNT1 0xFE430018
#define TCR1 0xFE43001C
#define TCOR2 0xFE430020
#define TCNT2 0xFE430024
#define TCR2 0xFE430028
#define TCPR2 0xFE43002C
/* ETHER, GETHER MAC address */
struct ether_mac_regs {
unsigned int reserved[114];
unsigned int mahr;
unsigned int reserved2;
unsigned int malr;
};
#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
/* GETHER */
struct gether_control_regs {
unsigned int gbecont;
};
#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
#define GBECONT_RMII1 0x00020000
#define GBECONT_RMII0 0x00010000
/* USB0/1 */
struct usb_common_regs {
unsigned short reserved[129];
unsigned short suspmode;
};
#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
struct usb0_phy_regs {
unsigned short reset;
unsigned short reserved[4];
unsigned short portsel;
};
#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
struct usb1_port_regs {
unsigned int port1sel;
unsigned int reserved;
unsigned int usb1intsts;
};
#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
struct usb1_alignment_regs {
unsigned int ehcidatac; /* 0xfe4fe018 */
unsigned int reserved[63];
unsigned int ohcidatac;
};
#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
/* GCTRL, GRA */
struct gctrl_regs {
unsigned int wprotect;
unsigned int gplldiv;
unsigned int gracr2; /* GRA */
unsigned int gracr3; /* GRA */
unsigned int reserved[4];
unsigned int fcntcr1;
unsigned int fcntcr2;
unsigned int reserved2[2];
unsigned int gpll1div;
unsigned int vcompsel;
unsigned int reserved3[62];
unsigned int fdlmon;
unsigned int reserved4[2];
unsigned int flcrmon;
unsigned int reserved5[944];
unsigned int spibootcan;
};
#define GCTRL_BASE ((struct gctrl_regs *)0xffc10000)
/* PCIe setup */
struct pcie_setup_regs {
unsigned int pbictl0;
unsigned int gradevctl;
unsigned int reserved[2];
unsigned int bmcinf[6];
unsigned int reserved2[118];
unsigned int idset[2];
unsigned int subidset;
unsigned int reserved3[2];
unsigned int linkconfset[4];
unsigned int trsid;
unsigned int reserved4[6];
unsigned int toutset;
unsigned int reserved5[7];
unsigned int lad0;
unsigned int ladmsk0;
unsigned int lad1;
unsigned int ladmsk1;
unsigned int lad2;
unsigned int ladmsk2;
unsigned int lad3;
unsigned int ladmsk3;
unsigned int lad4;
unsigned int ladmsk4;
unsigned int lad5;
unsigned int ladmsk5;
unsigned int reserved6[94];
unsigned int vdmrxvid[2];
unsigned int reserved7;
unsigned int pbiintfr;
unsigned int pbiinten;
unsigned int msimap;
unsigned int barmap;
unsigned int baracsize;
unsigned int advserest;
unsigned int pbictl3;
unsigned int reserved8[8];
unsigned int pbictl1;
unsigned int scratch0;
unsigned int reserved9[6];
unsigned int pbictl2;
unsigned int reserved10;
unsigned int pbirev;
};
#define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000)
struct pcie_system_bus_regs {
unsigned int reserved[3];
unsigned int endictl0;
unsigned int endictl1;
};
#define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600)
/* PCIe-Bridge */
struct pciebrg_regs {
unsigned short ctrl_h8s;
unsigned short reserved[7];
unsigned short cp_addr;
unsigned short reserved2;
unsigned short cp_data;
unsigned short reserved3;
unsigned short cp_ctrl;
};
#define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000)
/* CPU version */
#define CCN_PRR 0xff000044
#define prr_mask(_val) ((_val >> 4) & 0xff)
#define PRR_SH7757_B0 0x10
#define PRR_SH7757_C0 0x11
#define is_sh7757_b0(_val) \
({ \
int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \
__ret; \
})
#endif /* ifndef __ASSEMBLY__ */
#endif /* _ASM_CPU_SH7757_H_ */
#
# Copyright (C) 2011 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := sh7757lcr.o spi-boot.o
SOBJS := lowlevel_init.o
$(LIB): $(obj).depend $(COBJS) $(SOBJS)
$(call cmd_link_o_target, $(COBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* Copyright (C) 2011 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
.macro or32, addr, data
mov.l \addr, r1
mov.l \data, r0
mov.l @r1, r2
or r2, r0
mov.l r0, @r1
.endm
.macro wait_DBCMD
mov.l DBWAIT_A, r0
mov.l @r0, r1
.endm
.global lowlevel_init
.section .spiboot1.text
.align 2
lowlevel_init:
/*------- GPIO -------*/
write8 PGDR_A, PGDR_D /* eMMC power off */
write16 PACR_A, PACR_D
write16 PBCR_A, PBCR_D
write16 PCCR_A, PCCR_D
write16 PDCR_A, PDCR_D
write16 PECR_A, PECR_D
write16 PFCR_A, PFCR_D
write16 PGCR_A, PGCR_D
write16 PHCR_A, PHCR_D
write16 PICR_A, PICR_D
write16 PJCR_A, PJCR_D
write16 PKCR_A, PKCR_D
write16 PLCR_A, PLCR_D
write16 PMCR_A, PMCR_D
write16 PNCR_A, PNCR_D
write16 POCR_A, POCR_D
write16 PQCR_A, PQCR_D
write16 PRCR_A, PRCR_D
write16 PSCR_A, PSCR_D
write16 PTCR_A, PTCR_D
write16 PUCR_A, PUCR_D
write16 PVCR_A, PVCR_D
write16 PWCR_A, PWCR_D
write16 PXCR_A, PXCR_D
write16 PYCR_A, PYCR_D
write16 PZCR_A, PZCR_D
write16 PSEL0_A, PSEL0_D
write16 PSEL1_A, PSEL1_D
write16 PSEL2_A, PSEL2_D
write16 PSEL3_A, PSEL3_D
write16 PSEL4_A, PSEL4_D
write16 PSEL5_A, PSEL5_D
write16 PSEL6_A, PSEL6_D
write16 PSEL7_A, PSEL7_D
write16 PSEL8_A, PSEL8_D
bra exit_gpio
nop
.align 4
/*------- GPIO -------*/
PGDR_A: .long 0xffec0040
PACR_A: .long 0xffec0000
PBCR_A: .long 0xffec0002
PCCR_A: .long 0xffec0004
PDCR_A: .long 0xffec0006
PECR_A: .long 0xffec0008
PFCR_A: .long 0xffec000a
PGCR_A: .long 0xffec000c
PHCR_A: .long 0xffec000e
PICR_A: .long 0xffec0010
PJCR_A: .long 0xffec0012
PKCR_A: .long 0xffec0014
PLCR_A: .long 0xffec0016
PMCR_A: .long 0xffec0018
PNCR_A: .long 0xffec001a
POCR_A: .long 0xffec001c
PQCR_A: .long 0xffec0020
PRCR_A: .long 0xffec0022
PSCR_A: .long 0xffec0024
PTCR_A: .long 0xffec0026
PUCR_A: .long 0xffec0028
PVCR_A: .long 0xffec002a
PWCR_A: .long 0xffec002c
PXCR_A: .long 0xffec002e
PYCR_A: .long 0xffec0030
PZCR_A: .long 0xffec0032
PSEL0_A: .long 0xffec0070
PSEL1_A: .long 0xffec0072
PSEL2_A: .long 0xffec0074
PSEL3_A: .long 0xffec0076
PSEL4_A: .long 0xffec0078
PSEL5_A: .long 0xffec007a
PSEL6_A: .long 0xffec007c
PSEL7_A: .long 0xffec0082
PSEL8_A: .long 0xffec0084
PGDR_D: .long 0x80
PACR_D: .long 0x0000
PBCR_D: .long 0x0001
PCCR_D: .long 0x0000
PDCR_D: .long 0x0000
PECR_D: .long 0x0000
PFCR_D: .long 0x0000
PGCR_D: .long 0x0000
PHCR_D: .long 0x0000
PICR_D: .long 0x0000
PJCR_D: .long 0x0000
PKCR_D: .long 0x0003
PLCR_D: .long 0x0000
PMCR_D: .long 0x0000
PNCR_D: .long 0x0000
POCR_D: .long 0x0000
PQCR_D: .long 0xc000
PRCR_D: .long 0x0000
PSCR_D: .long 0x0000
PTCR_D: .long 0x0000
#if defined(CONFIG_SH7757_OFFSET_SPI)
PUCR_D: .long 0x0055
#else
PUCR_D: .long 0x0000
#endif
PVCR_D: .long 0x0000
PWCR_D: .long 0x0000
PXCR_D: .long 0x0000
PYCR_D: .long 0x0000
PZCR_D: .long 0x0000
PSEL0_D: .long 0xfe00
PSEL1_D: .long 0x0000
PSEL2_D: .long 0x3000
PSEL3_D: .long 0xff00
PSEL4_D: .long 0x771f
PSEL5_D: .long 0x0ffc
PSEL6_D: .long 0x00ff
PSEL7_D: .long 0xfc00
PSEL8_D: .long 0x0000
.align 2
exit_gpio:
mov #0, r14
mova 2f, r0
mov.l PC_MASK, r1
tst r0, r1
bf 2f
bra exit_pmb
nop
.align 2
/* If CPU runs on SDRAM, PC is 0x8???????. */
PC_MASK: .long 0x20000000
2:
mov #1, r14
mov.l EXPEVT_A, r0
mov.l @r0, r0
mov.l EXPEVT_POWER_ON_RESET, r1
cmp/eq r0, r1
bt 1f
/*
* If EXPEVT value is manual reset or tlb multipul-hit,
* initialization of DDR3IF is not necessary.
*/
bra exit_ddr
nop
1:
/* For Core Reset */
mov.l DBACEN_A, r0
mov.l @r0, r0
cmp/eq #0, r0
bt 3f
/*
* If DBACEN == 1(DBSC was already enabled), we have to avoid the
* initialization of DDR3-SDRAM.
*/
bra exit_ddr
nop
3:
/*------- DDR3IF -------*/
/* oscillation stabilization time */
wait_timer WAIT_OSC_TIME
/* step 3 */
write32 DBCMD_A, DBCMD_RSTL_VAL
wait_timer WAIT_30US
/* step 4 */
write32 DBCMD_A, DBCMD_PDEN_VAL
/* step 5 */
write32 DBKIND_A, DBKIND_D
/* step 6 */
write32 DBCONF_A, DBCONF_D
write32 DBTR0_A, DBTR0_D
write32 DBTR1_A, DBTR1_D
write32 DBTR2_A, DBTR2_D
write32 DBTR3_A, DBTR3_D
write32 DBTR4_A, DBTR4_D
write32 DBTR5_A, DBTR5_D
write32 DBTR6_A, DBTR6_D
write32 DBTR7_A, DBTR7_D
write32 DBTR8_A, DBTR8_D
write32 DBTR9_A, DBTR9_D
write32 DBTR10_A, DBTR10_D
write32 DBTR11_A, DBTR11_D
write32 DBTR12_A, DBTR12_D
write32 DBTR13_A, DBTR13_D
write32 DBTR14_A, DBTR14_D
write32 DBTR15_A, DBTR15_D
write32 DBTR16_A, DBTR16_D
write32 DBTR17_A, DBTR17_D
write32 DBTR18_A, DBTR18_D
write32 DBTR19_A, DBTR19_D
write32 DBRNK0_A, DBRNK0_D
/* step 7 */
write32 DBPDCNT3_A, DBPDCNT3_D
/* step 8 */
write32 DBPDCNT1_A, DBPDCNT1_D
write32 DBPDCNT2_A, DBPDCNT2_D
write32 DBPDLCK_A, DBPDLCK_D
write32 DBPDRGA_A, DBPDRGA_D
write32 DBPDRGD_A, DBPDRGD_D
/* step 9 */
wait_timer WAIT_30US
/* step 10 */
write32 DBPDCNT0_A, DBPDCNT0_D
/* step 11 */
wait_timer WAIT_30US
wait_timer WAIT_30US
/* step 12 */
write32 DBCMD_A, DBCMD_WAIT_VAL
wait_DBCMD
/* step 13 */
write32 DBCMD_A, DBCMD_RSTH_VAL
wait_DBCMD
/* step 14 */
write32 DBCMD_A, DBCMD_WAIT_VAL
write32 DBCMD_A, DBCMD_WAIT_VAL
write32 DBCMD_A, DBCMD_WAIT_VAL
write32 DBCMD_A, DBCMD_WAIT_VAL
/* step 15 */
write32 DBCMD_A, DBCMD_PDXT_VAL
/* step 16 */
write32 DBCMD_A, DBCMD_MRS2_VAL
/* step 17 */
write32 DBCMD_A, DBCMD_MRS3_VAL
/* step 18 */
write32 DBCMD_A, DBCMD_MRS1_VAL
/* step 19 */
write32 DBCMD_A, DBCMD_MRS0_VAL
/* step 20 */
write32 DBCMD_A, DBCMD_ZQCL_VAL
write32 DBCMD_A, DBCMD_REF_VAL
write32 DBCMD_A, DBCMD_REF_VAL
wait_DBCMD
/* step 21 */
write32 DBADJ0_A, DBADJ0_D
write32 DBADJ1_A, DBADJ1_D
write32 DBADJ2_A, DBADJ2_D
/* step 22 */
write32 DBRFCNF0_A, DBRFCNF0_D
write32 DBRFCNF1_A, DBRFCNF1_D
write32 DBRFCNF2_A, DBRFCNF2_D
/* step 23 */
write32 DBCALCNF_A, DBCALCNF_D
/* step 24 */
write32 DBRFEN_A, DBRFEN_D
write32 DBCMD_A, DBCMD_SRXT_VAL
/* step 25 */
write32 DBACEN_A, DBACEN_D
/* step 26 */
wait_DBCMD
/* enable DDR-ECC */
write32 ECD_ECDEN_A, ECD_ECDEN_D
write32 ECD_INTSR_A, ECD_INTSR_D
write32 ECD_SPACER_A, ECD_SPACER_D
write32 ECD_MCR_A, ECD_MCR_D
bra exit_ddr
nop