Commit 8eceeb7f authored by Kim Phillips's avatar Kim Phillips
Browse files

mpc83xx: mpc8377erdb - change DDR settings to those from latest bsp



when using Linus' 83xx_defconfig, the mpc8377rdb would hang at boot
at either:

NET: Registered protocol family 16

or the

io scheduler cfq registered

message.  Fixing up these DDR settings appears to fix the problem.
Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
parent 27c5248d
...@@ -190,8 +190,8 @@ ...@@ -190,8 +190,8 @@
/* 0x3937d322 */ /* 0x3937d322 */
#define CONFIG_SYS_DDR_TIMING_2 0x02984cc8 #define CONFIG_SYS_DDR_TIMING_2 0x02984cc8
#define CONFIG_SYS_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \ #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x06090100 */ /* 0x06090100 */
#if defined(CONFIG_DDR_2T_TIMING) #if defined(CONFIG_DDR_2T_TIMING)
...@@ -205,7 +205,7 @@ ...@@ -205,7 +205,7 @@
/* 0x43000000 */ /* 0x43000000 */
#endif #endif
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
| (0x0442 << SDRAM_MODE_SD_SHIFT)) | (0x0442 << SDRAM_MODE_SD_SHIFT))
/* 0x04400442 */ /* DDR400 */ /* 0x04400442 */ /* DDR400 */
#define CONFIG_SYS_DDR_MODE2 0x00000000 #define CONFIG_SYS_DDR_MODE2 0x00000000
......
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