Commit 92a190aa authored by Alexey Brodkin's avatar Alexey Brodkin Committed by Tom Rini

net/designware - switch driver to phylib usage

With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
 * Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
 * Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
 * Support of custom phy initialization is now done with existing
"board_phy_config".

Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.

For example:
 * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
 * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be used

I believe there's no need now in "doc/README.designware_eth" because
user only needs to instantiate the driver with "designware_initialize"
whose prototype exists in "include/netdev.h".

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
parent 27ee59af
...@@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis) ...@@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis)
if (CONFIG_DW_PORTS & 1) { if (CONFIG_DW_PORTS & 1) {
static const unsigned short pins[] = P_RMII0; static const unsigned short pins[] = P_RMII0;
if (!peripheral_request_list(pins, "emac0")) if (!peripheral_request_list(pins, "emac0"))
ret += designware_initialize(0, EMAC0_MACCFG, 1, 0); ret += designware_initialize(EMAC0_MACCFG, 0);
} }
if (CONFIG_DW_PORTS & 2) { if (CONFIG_DW_PORTS & 2) {
static const unsigned short pins[] = P_RMII1; static const unsigned short pins[] = P_RMII1;
if (!peripheral_request_list(pins, "emac1")) if (!peripheral_request_list(pins, "emac1"))
ret += designware_initialize(1, EMAC1_MACCFG, 1, 0); ret += designware_initialize(EMAC1_MACCFG, 0);
} }
return ret; return ret;
......
...@@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis) ...@@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH) #if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII; u32 interface = PHY_INTERFACE_MODE_MII;
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
interface) >= 0)
ret++; ret++;
#endif #endif
return ret; return ret;
......
...@@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis) ...@@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH) #if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII; u32 interface = PHY_INTERFACE_MODE_MII;
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
interface) >= 0)
ret++; ret++;
#endif #endif
#if defined(CONFIG_MACB) #if defined(CONFIG_MACB)
......
...@@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis) ...@@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DESIGNWARE_ETH) #if defined(CONFIG_DESIGNWARE_ETH)
u32 interface = PHY_INTERFACE_MODE_MII; u32 interface = PHY_INTERFACE_MODE_MII;
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
interface) >= 0)
ret++; ret++;
#endif #endif
#if defined(CONFIG_MACB) #if defined(CONFIG_MACB)
......
...@@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis) ...@@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_DW_AUTONEG) #if defined(CONFIG_DW_AUTONEG)
interface = PHY_INTERFACE_MODE_GMII; interface = PHY_INTERFACE_MODE_GMII;
#endif #endif
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
interface) >= 0)
ret++; ret++;
#endif #endif
return ret; return ret;
......
...@@ -67,31 +67,32 @@ void board_nand_init(void) ...@@ -67,31 +67,32 @@ void board_nand_init(void)
fsmc_nand_init(nand); fsmc_nand_init(nand);
} }
int designware_board_phy_init(struct eth_device *dev, int phy_addr, int board_phy_config(struct phy_device *phydev)
int (*mii_write)(struct eth_device *, u8, u8, u16),
int dw_reset_phy(struct eth_device *))
{ {
/* Extended PHY control 1, select GMII */ /* Extended PHY control 1, select GMII */
mii_write(dev, phy_addr, 23, 0x0020); phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
/* Software reset necessary after GMII mode selction */ /* Software reset necessary after GMII mode selction */
dw_reset_phy(dev); phy_reset(phydev);
/* Enable extended page register access */ /* Enable extended page register access */
mii_write(dev, phy_addr, 31, 0x0001); phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
/* 17e: Enhanced LED behavior, needs to be written twice */ /* 17e: Enhanced LED behavior, needs to be written twice */
mii_write(dev, phy_addr, 17, 0x09ff); phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
mii_write(dev, phy_addr, 17, 0x09ff); phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
/* 16e: Enhanced LED method select */ /* 16e: Enhanced LED method select */
mii_write(dev, phy_addr, 16, 0xe0ea); phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
/* Disable extended page register access */ /* Disable extended page register access */
mii_write(dev, phy_addr, 31, 0x0000); phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
/* Enable clock output pin */ /* Enable clock output pin */
mii_write(dev, phy_addr, 18, 0x0049); phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0; return 0;
} }
...@@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis) ...@@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis)
{ {
int ret = 0; int ret = 0;
if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, if (designware_initialize(CONFIG_SPEAR_ETHBASE,
PHY_INTERFACE_MODE_GMII) >= 0) PHY_INTERFACE_MODE_GMII) >= 0)
ret++; ret++;
......
This driver supports Designware Ethernet Controller provided by Synopsis.
The driver is enabled by CONFIG_DESIGNWARE_ETH.
The driver has been developed and tested on SPEAr platforms. By default, the
MDIO interface works at 100/Full. #defining the below options in board
configuration file changes this behavior.
Call an subroutine from respective board/.../board.c
designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
The various options suported by the driver are
1. CONFIG_DW_ALTDESCRIPTOR
Define this to use the Alternate/Enhanced Descriptor configurations.
1. CONFIG_DW_AUTONEG
Define this to autonegotiate with the host before proceeding with mac
level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
and CONFIG_DW_DUPLEXHALF.
2. CONFIG_DW_SPEED10M
Define this to change the default behavior from 100Mbps to 10Mbps.
3. CONFIG_DW_DUPLEXHALF
Define this to change the default behavior from Full Duplex to Half.
4. CONFIG_DW_SEARCH_PHY
Define this to search the phy address. This would overwrite the value
passed as 3rd arg from designware_initialize routine.
...@@ -17,7 +17,75 @@ ...@@ -17,7 +17,75 @@
#include <asm/io.h> #include <asm/io.h>
#include "designware.h" #include "designware.h"
static int configure_phy(struct eth_device *dev); #if !defined(CONFIG_PHYLIB)
# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
#endif
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
struct eth_mac_regs *mac_p = bus->priv;
ulong start;
u16 miiaddr;
int timeout = CONFIG_MDIO_TIMEOUT;
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
((reg << MIIREGSHIFT) & MII_REGMSK);
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
start = get_timer(0);
while (get_timer(start) < timeout) {
if (!(readl(&mac_p->miiaddr) & MII_BUSY))
return readl(&mac_p->miidata);
udelay(10);
};
return -1;
}
static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 val)
{
struct eth_mac_regs *mac_p = bus->priv;
ulong start;
u16 miiaddr;
int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
writel(val, &mac_p->miidata);
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
start = get_timer(0);
while (get_timer(start) < timeout) {
if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
ret = 0;
break;
}
udelay(10);
};
return ret;
}
static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p)
{
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate MDIO bus\n");
return -1;
}
bus->read = dw_mdio_read;
bus->write = dw_mdio_write;
sprintf(bus->name, name);
bus->priv = (void *)mac_regs_p;
return mdio_register(bus);
}
static void tx_descs_init(struct eth_device *dev) static void tx_descs_init(struct eth_device *dev)
{ {
...@@ -83,53 +151,59 @@ static void rx_descs_init(struct eth_device *dev) ...@@ -83,53 +151,59 @@ static void rx_descs_init(struct eth_device *dev)
priv->rx_currdescnum = 0; priv->rx_currdescnum = 0;
} }
static void descs_init(struct eth_device *dev) static int dw_write_hwaddr(struct eth_device *dev)
{ {
tx_descs_init(dev); struct dw_eth_dev *priv = dev->priv;
rx_descs_init(dev); struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 macid_lo, macid_hi;
u8 *mac_id = &dev->enetaddr[0];
macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
(mac_id[3] << 24);
macid_hi = mac_id[4] + (mac_id[5] << 8);
writel(macid_hi, &mac_p->macaddr0hi);
writel(macid_lo, &mac_p->macaddr0lo);
return 0;
} }
static int mac_reset(struct eth_device *dev) static void dw_adjust_link(struct eth_mac_regs *mac_p,
struct phy_device *phydev)
{ {
struct dw_eth_dev *priv = dev->priv; u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
ulong start; if (!phydev->link) {
int timeout = CONFIG_MACRESET_TIMEOUT; printf("%s: No link.\n", phydev->dev->name);
return;
}
writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); if (phydev->speed != 1000)
conf |= MII_PORTSELECT;
if (priv->interface != PHY_INTERFACE_MODE_RGMII) if (phydev->speed == 100)
writel(MII_PORTSELECT, &mac_p->conf); conf |= FES_100;
start = get_timer(0); if (phydev->duplex)
while (get_timer(start) < timeout) { conf |= FULLDPLXMODE;
if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
return 0;
/* Try again after 10usec */ writel(conf, &mac_p->conf);
udelay(10);
};
return -1; printf("Speed: %d, %s duplex%s\n", phydev->speed,
(phydev->duplex) ? "full" : "half",
(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
} }
static int dw_write_hwaddr(struct eth_device *dev) static void dw_eth_halt(struct eth_device *dev)
{ {
struct dw_eth_dev *priv = dev->priv; struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 macid_lo, macid_hi; struct eth_dma_regs *dma_p = priv->dma_regs_p;
u8 *mac_id = &dev->enetaddr[0];
macid_lo = mac_id[0] + (mac_id[1] << 8) + \ writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
(mac_id[2] << 16) + (mac_id[3] << 24); writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
macid_hi = mac_id[4] + (mac_id[5] << 8);
writel(macid_hi, &mac_p->macaddr0hi); phy_shutdown(priv->phydev);
writel(macid_lo, &mac_p->macaddr0lo);
return 0;
} }
static int dw_eth_init(struct eth_device *dev, bd_t *bis) static int dw_eth_init(struct eth_device *dev, bd_t *bis)
...@@ -137,55 +211,43 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) ...@@ -137,55 +211,43 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
struct dw_eth_dev *priv = dev->priv; struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 conf; unsigned int start;
if (priv->phy_configured != 1) writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
configure_phy(dev);
/* Print link status only once */ start = get_timer(0);
if (!priv->link_printed) { while (readl(&dma_p->busmode) & DMAMAC_SRST) {
printf("ENET Speed is %d Mbps - %s duplex connection\n", if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT)
priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); return -1;
priv->link_printed = 1;
}
/* Reset ethernet hardware */ mdelay(100);
if (mac_reset(dev) < 0) };
return -1;
/* Resore the HW MAC address as it has been lost during MAC reset */ /* Soft reset above clears HW address registers.
* So we have to set it here once again */
dw_write_hwaddr(dev); dw_write_hwaddr(dev);
writel(FIXEDBURST | PRIORXTX_41 | BURST_16, rx_descs_init(dev);
&dma_p->busmode); tx_descs_init(dev);
writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
TXSECONDFRAME, &dma_p->opmode);
conf = FRAMEBURSTENABLE | DISABLERXOWN; writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
if (priv->speed != 1000) writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
conf |= MII_PORTSELECT; &dma_p->opmode);
if ((priv->interface != PHY_INTERFACE_MODE_MII) && writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
(priv->interface != PHY_INTERFACE_MODE_GMII)) {
if (priv->speed == 100) /* Start up the PHY */
conf |= FES_100; if (phy_startup(priv->phydev)) {
printf("Could not initialize PHY %s\n",
priv->phydev->dev->name);
return -1;
} }
if (priv->duplex == FULL) dw_adjust_link(mac_p, priv->phydev);
conf |= FULLDPLXMODE;
writel(conf, &mac_p->conf);
descs_init(dev); if (!priv->phydev->link)
return -1;
/*
* Start/Enable xfer at dma as well as mac level
*/
writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
...@@ -267,251 +329,30 @@ static int dw_eth_recv(struct eth_device *dev) ...@@ -267,251 +329,30 @@ static int dw_eth_recv(struct eth_device *dev)
return length; return length;
} }
static void dw_eth_halt(struct eth_device *dev) static int dw_phy_init(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
mac_reset(dev);
priv->tx_currdescnum = priv->rx_currdescnum = 0;
}
static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
{ {
struct dw_eth_dev *priv = dev->priv; struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p; struct phy_device *phydev;
ulong start; int mask = 0xffffffff;
u32 miiaddr;
int timeout = CONFIG_MDIO_TIMEOUT;
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
((reg << MIIREGSHIFT) & MII_REGMSK);
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
start = get_timer(0);
while (get_timer(start) < timeout) {
if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
*val = readl(&mac_p->miidata);
return 0;
}
/* Try again after 10usec */ #ifdef CONFIG_PHY_ADDR
udelay(10); mask = 1 << CONFIG_PHY_ADDR;
};
return -1;
}
static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
ulong start;
u32 miiaddr;
int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
u16 value;
writel(val, &mac_p->miidata);
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
start = get_timer(0);
while (get_timer(start) < timeout) {
if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
ret = 0;
break;
}
/* Try again after 10usec */
udelay(10);
};
/* Needed as a fix for ST-Phy */
eth_mdio_read(dev, addr, reg, &value);
return ret;
}
#if defined(CONFIG_DW_SEARCH_PHY)
static int find_phy(struct eth_device *dev)
{
int phy_addr = 0;
u16 ctrl, oldctrl;
do {
eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
oldctrl = ctrl & BMCR_ANENABLE;
ctrl ^= BMCR_ANENABLE;
eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
ctrl &= BMCR_ANENABLE;
if (ctrl == oldctrl) {
phy_addr++;
} else {
ctrl ^= BMCR_ANENABLE;
eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
return phy_addr;
}
} while (phy_addr < 32);
return -1;
}
#endif #endif
static int dw_reset_phy(struct eth_device *dev) phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
{ if (!phydev)
struct dw_eth_dev *priv = dev->priv;
u16 ctrl;
ulong start;
int timeout = CONFIG_PHYRESET_TIMEOUT;
u32 phy_addr = priv->address;
eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
start = get_timer(0);
while (get_timer(start) < timeout) {
eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
if (!(ctrl & BMCR_RESET))
break;
/* Try again after 10usec */
udelay(10);
};
if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
return -1; return -1;
#ifdef CONFIG_PHY_RESET_DELAY phydev->supported &= PHY_GBIT_FEATURES;
udelay(CONFIG_PHY_RESET_DELAY); phydev->advertising = phydev->supported;
#endif
return 0;
}
/* priv->phydev = phydev;
* Add weak default function for board specific PHY configuration phy_config(phydev);
*/
int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr,
int (*mii_write)(struct eth_device *, u8, u8, u16),
int dw_reset_phy(struct eth_device *))
{