Commit 94568b60 authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Update for SC520 board.

Patch by David Updegraff, 02 Dec 2005
parent 2f6fa46d
......@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4:
======================================================================
* Update for SC520 board.
Patch by David Updegraff, 02 Dec 2005
* Fixed common.h spelling error.
Patch by Cory Tusar, 30 Nov 2005
......
......@@ -31,7 +31,9 @@
#include <common.h>
#include <config.h>
#include <pci.h>
#ifdef CONFIG_SC520_SSI
#include <ssi.h>
#endif
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/ic/sc520.h>
......@@ -143,7 +145,15 @@ unsigned long init_sc520_dram(void)
u32 dram_present=0;
u32 dram_ctrl;
#ifdef CFG_SDRAM_DRCTMCTL
/* these memory control registers are set up in the assember part,
* in sc520_asm.S, during 'mem_init'. If we muck with them here,
* after we are running a stack in RAM, we have troubles. Besides,
* these refresh and delay values are better ? simply specified
* outright in the include/configs/{cfg} file since the HW designer
* simply dictates it.
*/
#else
int val;
int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
......@@ -162,6 +172,7 @@ unsigned long init_sc520_dram(void)
} else {
val = 3; /* 62.4us */
}
write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
val = read_mmcr_byte(SC520_DRCTMCTL);
......@@ -181,13 +192,12 @@ unsigned long init_sc520_dram(void)
val |= 1;
}
write_mmcr_byte(SC520_DRCTMCTL, val);
#endif
/* We read-back the configuration of the dram
* controller that the assembly code wrote */
dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
bd->bi_dram[0].start = 0;
if (dram_ctrl & 0x80) {
/* bank 0 enabled */
......@@ -274,7 +284,7 @@ int pci_sc520_set_irq(int pci_pin, int irq)
{
int i;
# if 0
# if 1
printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
#endif
if (irq < 0 || irq > 15) {
......
......@@ -113,6 +113,7 @@
.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
......@@ -459,6 +460,12 @@ emptybank:
incl %edi
loop cleanuplp
#if defined CFG_SDRAM_DRCTMCTL
/* just have your hardware desinger _GIVE_ you what you need here! */
movl $DRCTMCTL, %edi
movb $CFG_SDRAM_DRCTMCTL,%al
movb (%edi), %al
#else
#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
/* set the CAS latency now since it is hard to do
* when we run from the RAM */
......@@ -470,7 +477,8 @@ emptybank:
#ifdef CFG_SDRAM_CAS_LATENCY_3T
orb $0x10, %al
#endif
movb %al, (%edi)
movb %al, (%edi)
#endif
#endif
movl $DRCCTL, %edi /* DRAM Control register */
movb $0x3,%al /* Load mode register cmd */
......@@ -528,9 +536,49 @@ bank0: movl (%edi), %eax
shll $22, %eax
movl %eax, %ebx
done: movl %ebx, %eax
done:
movl %ebx, %eax
#if CFG_SDRAM_ECC_ENABLE
/* A nominal memory test: just a byte at each address line */
movl %eax, %ecx
shrl $0x1, %ecx
movl $0x1, %edi
memtest0:
movb $0xa5, (%edi)
cmpb $0xa5, (%edi)
jne out
shrl $1, %ecx
andl %ecx,%ecx
jz set_ecc
shll $1, %edi
jmp memtest0
set_ecc:
/* clear all ram with a memset */
movl %eax, %ecx
xorl %esi, %esi
xorl %edi, %edi
xorl %eax, %eax
shrl $2, %ecx
cld
rep stosl
/* enable read, write buffers */
movb $0x11, %al
movl $DBCTL, %edi
movb %al, (%edi)
/* enable NMI mapping for ECC */
movl $ECCINT, %edi
mov $0x10, %al
movb %al, (%edi)
/* Turn on ECC */
movl $ECCCTL, %edi
mov $0x05, %al
movb %al, (%edi)
#endif
out:
movl %ebx, %eax
jmp *%ebp
#endif /* CONFIG_SC520 */
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