Commit 9458f6d8 authored by Roy Zang's avatar Roy Zang Committed by Andy Fleming
Browse files

T4/serdes: fix the serdes clock frequency



Reverse the bit sequence to set and display serdes clock frequency
correctly. The correct bit maps in BRDCFG2 are
0	1	2	3	4	5	6	7
S1RATE[1:0]	S2RATE[1:0] 	S3RATE[1:0] 	S4RATE[1:0]
Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
parent 3e4c3137
......@@ -110,7 +110,7 @@ int checkboard(void)
for (i = 0; i < MAX_SERDES; i++) {
static const char *freq[] = {
"100", "125", "156.25", "161.1328125"};
unsigned int clock = (sw >> (2 * i)) & 3;
unsigned int clock = (sw >> (6 - 2 * i)) & 3;
printf("SERDES%u=%sMHz ", i+1, freq[clock]);
}
......@@ -357,7 +357,7 @@ int misc_init_r(void)
sw = QIXIS_READ(brdcfg[2]);
for (i = 0; i < MAX_SERDES; i++) {
unsigned int clock = (sw >> (2 * i)) & 3;
unsigned int clock = (sw >> (6 - 2 * i)) & 3;
switch (clock) {
case 0:
actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment