Commit 96fdbec2 authored by R Sricharan's avatar R Sricharan Committed by Albert ARIBAUD
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ARM: mmu: Introduce weak dram_bank_setup function



Introduce a weak version of dram_bank_setup function
to allow a platform specific function.

This is used in the subsequent patch to setup dram region
without 'XN' attribute in order to enable the region
under client permissions.
Signed-off-by: default avatarR Sricharan <r.sricharan@ti.com>
Cc: Vincent Stehle <v-stehle@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
parent dfa41387
......@@ -43,6 +43,7 @@ void l2_cache_enable(void);
void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option);
void dram_bank_mmu_setup(int bank);
/*
* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
* use that value for aligning DMA buffers unless the board config has specified
......
......@@ -23,6 +23,8 @@
#include <common.h>
#include <asm/system.h>
#include <asm/cache.h>
#include <linux/compiler.h>
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
......@@ -77,7 +79,7 @@ void mmu_set_region_dcache_behaviour(u32 start, int size,
mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
}
static inline void dram_bank_mmu_setup(int bank)
__weak void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
int i;
......
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