Commit 97bf85d7 authored by Daniel Hellstrom's avatar Daniel Hellstrom Committed by Stefan Roese
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MTD/CFI: flash_read64 is defined a weak function (for SPARC)



SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address.
SPARC CPUs implement flash_read64 which calls __raw_readq.

For current SPARC architectures (LEON2 and LEON3) each read from the
FLASH must lead to a cache miss. This is because FLASH can not be set
non-cacheable since program code resides there, and alternatively disabling
cache is poor from performance view, or doing a cache flush between each
read is even poorer.

Forcing a cache miss on a SPARC is done by a special instruction "lda" -
load alternative space, the alternative space number (ASI) is processor
implementation spcific and can be found by including <asm/processor.h>.
Signed-off-by: default avatarDaniel Hellstrom <daniel@gaisler.com>
parent 90447ecb
......@@ -239,12 +239,14 @@ static u32 flash_read32(void *addr)
return __raw_readl(addr);
}
static u64 flash_read64(void *addr)
static u64 __flash_read64(void *addr)
{
/* No architectures currently implement __raw_readq() */
return *(volatile u64 *)addr;
}
u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
/*-----------------------------------------------------------------------
*/
#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
......
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