Commit 989c5f0a authored by Tang Yuantian's avatar Tang Yuantian Committed by York Sun
Browse files

armv8: Add sata support on Layerscape ARMv8 board



Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: default avatarTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
parent 3a4800a5
......@@ -6,6 +6,8 @@
#include <common.h>
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
......@@ -157,7 +159,44 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
}
#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
{
struct ccsr_ahci __iomem *ccsr_ahci;
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(0);
return 0;
}
#endif
#elif defined(CONFIG_LS1043A)
#ifdef CONFIG_SCSI_AHCI_PLAT
int sata_init(void)
{
struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA);
scsi_scan(0);
return 0;
}
#endif
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
......@@ -183,6 +222,10 @@ void fsl_lsch2_early_init_f(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
#endif
return 0;
}
#endif
......@@ -69,6 +69,10 @@
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
/* SATA */
#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
......
......@@ -51,6 +51,37 @@ struct cpu_type {
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
#define AHCI_PORT_PHY_2_CFG 0x28184d1f
#define AHCI_PORT_PHY_3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029
/* AHCI (sata) register map */
struct ccsr_ahci {
u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
u32 pcfg; /* port config */
u32 ppcfg; /* port phy1 config */
u32 pp2c; /* port phy2 config */
u32 pp3c; /* port phy3 config */
u32 pp4c; /* port phy4 config */
u32 pp5c; /* port phy5 config */
u32 axicc; /* AXI cache control */
u32 paxic; /* port AXI config */
u32 axipc; /* AXI PROT control */
u32 ptc; /* port Trans Config */
u32 pts; /* port Trans Status */
u32 plc; /* port link config */
u32 plc1; /* port link config1 */
u32 plc2; /* port link config2 */
u32 pls; /* port link status */
u32 pls1; /* port link status1 */
u32 pcmdc; /* port CMD config */
u32 ppcs; /* port phy control status */
u32 pberr; /* port 0/1 BIST error */
u32 cmds; /* port 0/1 CMD status error */
};
#ifdef CONFIG_FSL_LSCH3
void fsl_lsch3_early_init_f(void);
#elif defined(CONFIG_FSL_LSCH2)
......
......@@ -88,6 +88,23 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
#endif
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
/*
* IFC Definitions
*/
......
......@@ -40,6 +40,24 @@ unsigned long get_board_ddr_clk(void);
#endif
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
......
......@@ -42,6 +42,24 @@ unsigned long get_board_sys_clk(void);
#endif
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
......
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