Commit 9902c113 authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-uniphier

parents e5e88c65 11d3ede4
......@@ -690,15 +690,16 @@ config TARGET_COLIBRI_PXA270
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select CLK_UNIPHIER
select CPU_V7
select SUPPORT_SPL
select SPL
select OF_CONTROL
select SPL_OF_CONTROL
select DM
select SPL_DM
select DM_GPIO
select DM_SERIAL
select DM_I2C
select DM_MMC
help
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
......
......@@ -23,12 +23,6 @@
ranges;
interrupt-parent = <&intc>;
extbus: extbus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
};
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
......@@ -69,9 +63,16 @@
clocks = <&uart_clk>;
};
system-bus-controller@58c00000 {
compatible = "socionext,uniphier-system-bus-controller";
reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
mio: mioctrl@59810000 {
......
......@@ -51,6 +51,10 @@
status = "okay";
};
&sd {
status = "okay";
};
&usb0 {
status = "okay";
};
......
......@@ -56,6 +56,118 @@
cache-level = <2>;
};
port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port1x: gpio@55000010 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000010 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port2x: gpio@55000018 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000018 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port3x: gpio@55000020 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000020 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port4: gpio@55000028 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000028 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port5x: gpio@55000030 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000030 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port6x: gpio@55000038 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000038 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port7x: gpio@55000040 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000040 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port8x: gpio@55000048 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000048 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port9x: gpio@55000050 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000050 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port10x: gpio@55000058 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000058 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port11x: gpio@55000060 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000060 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port12x: gpio@55000068 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000068 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port13x: gpio@55000070 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000070 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port14x: gpio@55000078 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000078 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port16x: gpio@55000088 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000088 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
i2c0: i2c@58400000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";
......@@ -108,6 +220,31 @@
clock-frequency = <100000>;
};
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a400000 0x200>;
interrupts = <0 76 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio 0>;
bus-width = <4>;
};
emmc: sdhc@5a500000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a500000 0x200>;
interrupts = <0 78 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio 1>;
bus-width = <8>;
non-removable;
};
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
......
......@@ -53,6 +53,10 @@
status = "okay";
};
&sd {
status = "okay";
};
&usb0 {
status = "okay";
};
......
......@@ -69,6 +69,10 @@
status = "okay";
};
&sd {
status = "okay";
};
&usb0 {
status = "okay";
};
......
......@@ -54,6 +54,14 @@
status = "okay";
};
&sd {
status = "okay";
};
&sd1 {
status = "okay";
};
&usb0 {
status = "okay";
};
......
......@@ -64,6 +64,10 @@
status = "okay";
};
&emmc {
status = "okay";
};
&usb0 {
status = "okay";
};
......@@ -91,6 +95,14 @@
u-boot,dm-pre-reloc;
};
&mio {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
......@@ -98,3 +110,7 @@
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};
&pinctrl_emmc {
u-boot,dm-pre-reloc;
};
......@@ -64,6 +64,209 @@
cache-level = <2>;
};
port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port1x: gpio@55000010 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000010 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port2x: gpio@55000018 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000018 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port3x: gpio@55000020 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000020 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port4: gpio@55000028 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000028 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port5x: gpio@55000030 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000030 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port6x: gpio@55000038 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000038 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port7x: gpio@55000040 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000040 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port8x: gpio@55000048 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000048 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port9x: gpio@55000050 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000050 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port10x: gpio@55000058 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000058 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port11x: gpio@55000060 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000060 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port12x: gpio@55000068 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000068 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port13x: gpio@55000070 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000070 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port14x: gpio@55000078 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000078 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port17x: gpio@550000a0 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000a0 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port18x: gpio@550000a8 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000a8 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port19x: gpio@550000b0 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000b0 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port20x: gpio@550000b8 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000b8 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port21x: gpio@550000c0 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000c0 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port22x: gpio@550000c8 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000c8 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port23x: gpio@550000d0 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000d0 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port24x: gpio@550000d8 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000d8 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port25x: gpio@550000e0 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000e0 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port26x: gpio@550000e8 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000e8 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port27x: gpio@550000f0 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000f0 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port28x: gpio@550000f8 {
compatible = "socionext,uniphier-gpio";
reg = <0x550000f8 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port29x: gpio@55000100 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000100 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port30x: gpio@55000108 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000108 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
......@@ -140,6 +343,43 @@
clock-frequency = <400000>;
};
sd: sdhc@5a400000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a400000 0x200>;
interrupts = <0 76 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_1v8>;
clocks = <&mio 0>;
bus-width = <4>;
};
emmc: sdhc@5a500000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a500000 0x200>;
interrupts = <0 78 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_emmc>;
pinctrl-1 = <&pinctrl_emmc_1v8>;
clocks = <&mio 1>;
bus-width = <8>;
non-removable;
};
sd1: sdhc@5a600000 {
compatible = "socionext,uniphier-sdhc";
status = "disabled";
reg = <0x5a600000 0x200>;
interrupts = <0 85 4>;
pinctrl-names = "default", "1.8v";
pinctrl-0 = <&pinctrl_sd1>;
pinctrl-1 = <&pinctrl_sd1_1v8>;
clocks = <&mio 2>;
bus-width = <4>;
};
usb2: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
......
......@@ -47,6 +47,14 @@
status = "okay";
};
&emmc {
status = "okay";
};
&sd {
status = "okay";
};
/* for U-Boot only */
/ {
soc {
......
......@@ -76,6 +76,209 @@
cache-level = <3>;
};
port0x: gpio@55000008 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000008 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port1x: gpio@55000010 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000010 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port2x: gpio@55000018 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000018 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port3x: gpio@55000020 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000020 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port4: gpio@55000028 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000028 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port5x: gpio@55000030 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000030 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port6x: gpio@55000038 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000038 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port7x: gpio@55000040 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000040 0x8>;
gpio-controller;
#gpio-cells = <2>;
};
port8x: gpio@55000048 {
compatible = "socionext,uniphier-gpio";