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Commit 993cad93 authored by wdenk's avatar wdenk
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* Patches by Robert Schwebel, 26 Jun 2003: 

  - logdl
  - csb226
  - innokom

* Patch by Pantelis Antoniou, 25 Jun 2003:
  update NetVia with V2 board support
parent b783edae
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CHANGELOG
View file @ 993cad93
......@@ -2,6 +2,14 @@
Changes since U-Boot 0.3.1:
======================================================================
* Patches by Robert Schwebel, 26 Jun 2003:
- logdl
- csb226
- innokom
* Patch by Pantelis Antoniou, 25 Jun 2003:
update NetVia with V2 board support
* Header file cleanup for ARM
* Patch by Murray Jensen, 24 Jun 2003:
......
CREDITS
View file @ 993cad93
......@@ -146,6 +146,10 @@ N: Andreas Heppel
E: aheppel@sysgo.de
D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!]
N: August Hoeraendl
E: august.hoerandl@gmx.at
D: Support for the logodl board (PXA2xx)
N: Josh Huber
E: huber@alum.wpi.edu
D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
......@@ -256,7 +260,7 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor
N: Robert Schwebel
E: r.schwebel@pengutronix.de
D: Support for csb226 and innokom boards (xscale)
D: Support for csb226, logodl and innokom boards (PXA2xx)
N: Rob Taylor
E: robt@flyingpig.com
......@@ -294,3 +298,7 @@ N: Alex Zuepke
E: azu@sysgo.de
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA board support, ARTOS support.
MAKEALL
View file @ 993cad93
......@@ -31,12 +31,12 @@ LIST_8xx=" \
IP860 IVML24 IVML24_128 IVML24_256 \
IVMS8 IVMS8_128 IVMS8_256 KUP4K \
LANTEC lwmon MBX MBX860T \
MHPC MVS1 NETVIA NX823 \
pcu_e R360MPI RBC823 rmu \
RPXClassic RPXlite RRvision SM850 \
SPD823TS svm_sc8xx SXNI855T TOP860 \
TQM823L TQM823L_LCD TQM850L TQM855L \
TQM860L TTTech v37 \
MHPC MVS1 NETVIA NETVIA_V2 \
NX823 pcu_e R360MPI RBC823 \
rmu RPXClassic RPXlite RRvision \
SM850 SPD823TS svm_sc8xx SXNI855T \
TOP860 TQM823L TQM823L_LCD TQM850L \
TQM855L TQM860L TTTech v37 \
"
#########################################################################
......
Makefile
View file @ 993cad93
......@@ -302,8 +302,20 @@ MHPC_config: unconfig
MVS1_config : unconfig
@./mkconfig $(@:_config=) ppc mpc8xx mvs1
xtract_NETVIA = $(subst _V2,,$(subst _config,,$1))
NETVIA_V2_config \
NETVIA_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx netvia
@ >include/config.h
@[ -z "$(findstring NETVIA_config,$@)" ] || \
{ echo "#define CONFIG_NETVIA_VERSION 1" >>include/config.h ; \
echo "... Version 1" ; \
}
@[ -z "$(findstring NETVIA_V2_config,$@)" ] || \
{ echo "#define CONFIG_NETVIA_VERSION 2" >>include/config.h ; \
echo "... Version 2" ; \
}
@./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia
NX823_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx nx823
......
board/logodl/flash.c
View file @ 993cad93
This diff is collapsed.
board/logodl/logodl.c
View file @ 993cad93
/*
* (C) 2002 Kyle Harris <kharris@nexus-tech.net>, Nexus Technologies, Inc.
* (C) 2002 Marius Groeger <mgroeger@sysgo.de>, Sysgo GmbH
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
*
* See file CREDITS for list of people who contributed to this
* project.
......@@ -66,7 +66,7 @@ int dram_init (void)
}
/**
/**
* logodl_set_led: - switch LEDs on or off
*
* @param led: LED to switch (0,1)
......@@ -77,15 +77,15 @@ void logodl_set_led(int led, int state)
{
switch(led) {
case 0:
if (state==1) {
case 0:
if (state==1) {
CFG_LED_A_CR = CFG_LED_A_BIT;
} else if (state==0) {
CFG_LED_A_SR = CFG_LED_A_BIT;
}
break;
case 1:
case 1:
if (state==1) {
CFG_LED_B_CR = CFG_LED_B_BIT;
} else if (state==0) {
......@@ -93,7 +93,7 @@ void logodl_set_led(int led, int state)
}
break;
}
return;
}
......@@ -101,9 +101,9 @@ void logodl_set_led(int led, int state)
/**
* show_boot_progress: - indicate state of the boot process
*
* @param status: Status number - see README for details.
* @param status: Status number - see README for details.
*
* The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most
* The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most
* important states (1, 5, 15).
*/
......
board/netvia/flash.c
View file @ 993cad93
......@@ -44,11 +44,8 @@ unsigned long flash_init(void)
int i;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
......@@ -66,7 +63,22 @@ unsigned long flash_init(void)
flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
#ifdef CFG_ENV_ADDR_REDUND
flash_protect ( FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
&flash_info[0]);
#endif
flash_info[0].size = size;
......
board/netvia/netvia.c
View file @ 993cad93
......@@ -29,6 +29,17 @@
#include <common.h>
#include "mpc8xx.h"
/****************************************************************/
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* last value written to the external register; we cannot read back */
unsigned int last_er_val;
#endif
/****************************************************************/
/****************************************************************/
/* some sane bit macros */
#define _BD(_b) (1U << (31-(_b)))
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
......@@ -42,13 +53,11 @@
#define _B(_b) _BD(_b)
#define _BR(_l, _h) _BDR(_l, _h)
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/****************************************************************/
#define _NOT_USED_ 0xFFFFFFFF
/* ------------------------------------------------------------------------- */
/****************************************************************/
#define CS_0000 0x00000000
#define CS_0001 0x10000000
......@@ -208,7 +217,11 @@ const uint sdram_table[0x40] = {
int checkboard(void)
{
printf ("NETVIA\n");
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
printf ("NETVIA v1\n");
#else
printf ("NETVIA v2+\n");
#endif
return (0);
}
......@@ -275,25 +288,6 @@ long int initdram(int board_type)
udelay(10000);
/* do the ram test */
{
register unsigned long *rp;
register unsigned long v;
/* first fill */
for (rp = (unsigned long *)0; rp < (unsigned long *)SDRAM_MAX_SIZE; )
*rp++ = (unsigned long)rp;
/* now check */
for (rp = (unsigned long *)0; rp < (unsigned long *)SDRAM_MAX_SIZE; rp++) {
if ((v = *rp) != (unsigned long)rp) {
printf("ERROR at 0x%lx (0x%lx)\n", (unsigned long)rp, v);
return -1;
}
}
}
return (size);
}
......@@ -301,74 +295,141 @@ long int initdram(int board_type)
int misc_init_r(void)
{
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
last_er_val = 0xffffffff;
#endif
return(0);
}
/* ------------------------------------------------------------------------- */
/* GP = general purpose, SP = special purpose (on chip peripheral) */
/* bits that can have a special purpose or can be configured as inputs/outputs */
#define PA_MASK (_BWR(4, 9) | _BWR(12, 15))
#define PA_ODR_MASK (_BW(9) | _BW(12) | _BW(14))
#define PA_ODR_VAL 0
#define PA_GP_INMASK 0
#define PA_GP_OUTMASK (_BW(5) | _BW(14) | _BW(15))
#define PA_SP_OUTMASK 0
#define PA_GP_OUTMASK (_BW(5) | _BWR(14, 15))
#define PA_SP_MASK (_BW(4) | _BWR(6, 13))
#define PA_ODR_VAL 0
#define PA_GP_OUTVAL _BW(5)
#define PA_SP_OUTVAL 0
#define PA_SP_DIRVAL 0
#define PB_MASK (_BR(16, 19) | _BR(22, 31))
#define PB_ODR_MASK PB_MASK
#define PB_GP_INMASK _B(28)
#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
#define PB_SP_MASK _BR(22, 25)
#define PB_ODR_VAL 0
#define PB_GP_INMASK 0
#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _B(31))
#define PB_SP_OUTMASK _BR(28, 30)
#define PB_SP_OUTVAL _BR(28, 30)
#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _B(31))
#define PC_MASK _BWR(4, 15)
#define PC_SO_MASK (_BWR(6, 11) | _BWR(14, 15))
#define PC_SO_VAL 0
#define PC_INT_MASK PC_MASK
#define PC_INT_VAL 0
#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
#define PB_SP_DIRVAL 0
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13))
#define PC_GP_OUTMASK _BW(12)
#define PC_SP_OUTMASK 0
#define PC_SP_OUTVAL _BW(12)
#define PC_SP_MASK (_BW(4) | _BW(8))
#define PC_SOVAL 0
#define PC_INTVAL 0
#define PC_GP_OUTVAL 0
#define PC_SP_DIRVAL 0
#define PD_MASK _BWR(0, 15)
#define PD_GP_INMASK 0
#define PD_GP_OUTMASK _BWR(3, 15)
#define PD_SP_OUTMASK 0
#define PD_SP_MASK 0
#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15))
#define PD_SP_OUTVAL 0
#define PD_SP_DIRVAL 0
#elif CONFIG_NETVIA_VERSION >= 2
#define PC_GP_INMASK (_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15))
#define PC_GP_OUTMASK (_BW(6) | _BW(12))
#define PC_SP_MASK (_BW(4) | _BW(8))
#define PC_SOVAL 0
#define PC_INTVAL _BW(7)
#define PC_GP_OUTVAL (_BW(6) | _BW(12))
#define PC_SP_DIRVAL 0
#define PD_GP_INMASK 0
#define PD_GP_OUTMASK _BWR(3, 15)
#define PD_SP_MASK 0
#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(9) | _BW(11))
#define PD_SP_DIRVAL 0
#else
#error Unknown NETVIA board version.
#endif
int board_pre_init(void)
{
register volatile immap_t *immap = (immap_t *) CFG_IMMR;
register volatile iop8xx_t *ioport = &immap->im_ioport;
register volatile cpm8xx_t *cpm = &immap->im_cpm;
ioport->iop_padat = (ioport->iop_padat & ~PA_MASK) | PA_SP_OUTVAL | PA_GP_OUTVAL;
ioport->iop_paodr = (ioport->iop_paodr & ~PA_ODR_MASK) | PA_ODR_VAL;
ioport->iop_padir = (ioport->iop_padir & ~PA_GP_INMASK)| PA_SP_OUTMASK | PA_GP_OUTMASK;
ioport->iop_papar = (ioport->iop_papar & ~(PA_GP_INMASK & PA_GP_OUTMASK));
cpm->cp_pbdat = (ioport->iop_padat & ~PB_MASK) | PB_SP_OUTVAL | PB_GP_OUTVAL;
cpm->cp_pbodr = (ioport->iop_paodr & ~PB_ODR_MASK) | PB_ODR_VAL;
cpm->cp_pbdir = (ioport->iop_padir & ~PB_GP_INMASK)| PB_SP_OUTMASK | PB_GP_OUTMASK;
cpm->cp_pbpar = (ioport->iop_papar & ~(PB_GP_INMASK & PB_GP_OUTMASK));
ioport->iop_pcdat = (ioport->iop_pcdat & ~PC_MASK) | PC_SP_OUTVAL | PC_GP_OUTVAL;
ioport->iop_pcdir = (ioport->iop_pcdir & ~PC_GP_INMASK)| PC_SP_OUTMASK | PC_GP_OUTMASK;
ioport->iop_pcso = (ioport->iop_pcso & ~PC_SO_MASK) | PC_SO_VAL;
ioport->iop_pcint = (ioport->iop_pcint & ~PC_INT_MASK) | PC_INT_VAL;
ioport->iop_pcpar = (ioport->iop_pcpar & ~(PC_GP_INMASK & PC_GP_OUTMASK));
ioport->iop_pddat = (ioport->iop_pddat & ~PD_MASK) | PD_SP_OUTVAL | PD_GP_OUTVAL;
ioport->iop_pddir = (ioport->iop_pddir & ~PD_GP_INMASK)| PD_SP_OUTMASK | PD_GP_OUTMASK;
ioport->iop_pdpar = (ioport->iop_pdpar & ~(PD_GP_INMASK & PD_GP_OUTMASK));
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile iop8xx_t *ioport = &immap->im_ioport;
volatile cpm8xx_t *cpm = &immap->im_cpm;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* DSP0 chip select */
memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
/* DSP1 chip select */
memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
/* FPGA chip select */
memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK);
memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* NAND chip select */
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
/* kill this chip select */
memctl->memc_br2 &= ~BR_V; /* invalid */
/* external reg chip select */
memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
#endif
ioport->iop_padat = PA_GP_OUTVAL;
ioport->iop_paodr = PA_ODR_VAL;
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
ioport->iop_papar = PA_SP_MASK;
cpm->cp_pbdat = PB_GP_OUTVAL;
cpm->cp_pbodr = PB_ODR_VAL;
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
cpm->cp_pbpar = PB_SP_MASK;
ioport->iop_pcdat = PC_GP_OUTVAL;
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
ioport->iop_pcso = PC_SOVAL;
ioport->iop_pcint = PC_INTVAL;
ioport->iop_pcpar = PC_SP_MASK;
ioport->iop_pddat = PD_GP_OUTVAL;
ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
ioport->iop_pdpar = PD_SP_MASK;
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* external register init */
*(volatile uint *)ER_BASE = 0xFFFFFFFF;
#endif
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern void nand_probe(ulong physadr);
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
nand_dev_desc[0].name = "NetVia NAND flash";
puts("NAND: ");
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
board/netvia/u-boot.lds
View file @ 993cad93
......@@ -63,8 +63,8 @@ SECTIONS
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = env_offset;
common/environment.o (.ppcenv)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
......
board/rsdproto/flash_asm.S
View file @ 993cad93
......@@ -26,7 +26,7 @@
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
.globl ull_write
.globl ull_write
ull_write:
lfd 0,0(r4)
stfd 0,0(r3)
......
cpu/mpc8xx/scc.c
View file @ 993cad93
......@@ -494,14 +494,22 @@ static int scc_init(struct eth_device* dev, bd_t *bis)
#endif
#if defined(CONFIG_NETVIA)
#if defined(PB_ENET_PDN)
#if defined(PA_ENET_PDN)
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
immr->im_ioport.iop_padir |= PA_ENET_PDN;
immr->im_ioport.iop_padat |= PA_ENET_PDN;
#elif defined(PB_ENET_PDN)
immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
#elif defined(PC_ENET_PDN)
immr->im_cpm.cp_pcpar &= ~PC_ENET_PDN;
immr->im_cpm.cp_pcdir |= PC_ENET_PDN;
immr->im_cpm.cp_pcdat |= PC_ENET_PDN;
immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
#elif defined(PD_ENET_PDN)
immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
immr->im_ioport.iop_pddir |= PD_ENET_PDN;
immr->im_ioport.iop_pddat |= PD_ENET_PDN;
#endif
#endif
......
drivers/Makefile
View file @ 993cad93
......@@ -37,6 +37,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
pci.o pci_auto.o pci_indirect.o \
pcnet.o plb2800_eth.o \
s3c24x0_i2c.o sed13806.o serial.o \
serial_max3100.o \
smc91111.o smiLynxEM.o sym53c8xx.o \
ti_pci1410a.o tigon3.o w83c553f.o \
status_led.o
......
drivers/serial_max3100.c 0 → 100644
View file @ 993cad93
/*
* (C) Copyright 2003
*
* Pantelis Antoniou <panto@intracom.gr>
* Intracom S.A.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#ifdef CONFIG_MAX3100_SERIAL
/**************************************************************/
/* convienient macros */
#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT)
#define MAX3100_SPI_TXD(x) \
do { \
if (x) \
MAX3100_SPI_TXD_PORT |= MAX3100_SPI_TXD_BIT; \
else \
MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \
} while(0)
#define MAX3100_SPI_CLK(x) \
do { \
if (x) \
MAX3100_SPI_CLK_PORT |= MAX3100_SPI_CLK_BIT; \
else \
MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \
} while(0)
#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT)
#define MAX3100_CS(x) \
do { \
if (x) \
MAX3100_CS_PORT |= MAX3100_CS_BIT; \
else \
MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \
} while(0)
/**************************************************************/
/* MAX3100 definitions */
#define MAX3100_WC (3 << 14) /* write configuration */
#define MAX3100_RC (1 << 14) /* read configuration */
#define MAX3100_WD (2 << 14) /* write data */
#define MAX3100_RD (0 << 14) /* read data */
/* configuration register bits */
#define MAX3100_FEN (1 << 13) /* FIFO enable */
#define MAX3100_SHDN (1 << 12) /* shutdown bit */
#define MAX3100_TM (1 << 11) /* T bit irq mask */
#define MAX3100_RM (1 << 10) /* R bit irq mask */
#define MAX3100_PM (1 << 9) /* P bit irq mask */
#define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */
#define MAX3100_IR (1 << 7) /* IRDA timing mode */
#define MAX3100_ST (1 << 6) /* transmit stop bit */
#define MAX3100_PE (1 << 5) /* parity enable bit */
#define MAX3100_L (1 << 4) /* Length bit */
#define MAX3100_B_MASK (0x000F) /* baud rate bits mask */
#define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */
/* data register bits (write) */
#define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */
#define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */
/* data register bits (read) */
#define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */
#define MAX3100_FE (1 << 10) /* framing error when in normal mode */
#define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */
/* data register bits (both directions) */
#define MAX3100_R (1 << 15) /* receive bit */
#define MAX3100_T (1 << 14) /* transmit bit */
#define MAX3100_P (1 << 8) /* parity bit */
#define MAX3100_D_MASK 0x00FF /* data bits mask */
#define MAX3100_D(x) ((x) & 0x00FF) /* data bits */
/* these definitions are valid only for fOSC = 3.6864MHz */
#define MAX3100_B_230400 MAX3100_B(0)
#define MAX3100_B_115200 MAX3100_B(1)
#define MAX3100_B_57600 MAX3100_B(2)
#define MAX3100_B_38400 MAX3100_B(9)
#define MAX3100_B_19200 MAX3100_B(10)
#define MAX3100_B_9600 MAX3100_B(11)
#define MAX3100_B_4800 MAX3100_B(12)
#define MAX3100_B_2400 MAX3100_B(13)
#define MAX3100_B_1200 MAX3100_B(14)
#define MAX3100_B_600 MAX3100_B(15)
/**************************************************************/
static inline unsigned int max3100_transfer(unsigned int val)
{
unsigned int rx;
int b;
MAX3100_SPI_CLK(0);
MAX3100_CS(0);
rx = 0; b = 16;
while (--b >= 0) {
MAX3100_SPI_TXD(val & 0x8000);
val <<= 1;
MAX3100_SPI_CLK_TOGGLE();
udelay(1);
rx <<= 1;
if (MAX3100_SPI_RXD())
rx |= 1;
MAX3100_SPI_CLK_TOGGLE();