Commit 99fa97e9 authored by Andreas Bießmann's avatar Andreas Bießmann Committed by Reinhard Meyer
Browse files

at91rm9200ek: convert to at91



This patch removes some functionality from at91rm9200ek board but the
remaining functionality does now work with newer at91 code and
arm-relocation.

Currently missing features are:
 - dataflash booting (due to missing HW for testing)
 - MMC/SD-Card
 - first stage bootloader support is completely removed (not needed for
   NOR)

Cause this board was (some days ago) reference for all at91rm9200 based
boards this should be a good starting point to convert all remaining
at91rm9200 borads to at91 code. Aside from that this is a good base to
get some drivers between at91sam/at91rm/avr32 merged.
Signed-off-by: default avatarAndreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: default avatarReinhard Meyer <u-boot@emk-elektronik.de>
parent 1ba91ba2
......@@ -573,6 +573,10 @@ Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
Andreas Biemann <andreas.devel@gmail.com>
at91rm9200ek at91rm9200
Cliff Brake <cliff.brake@gmail.com>
pxa255_idp xscale
......
......@@ -27,11 +27,6 @@ LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += led.o
COBJS-y += misc.o
ifdef CONFIG_HAS_DATAFLASH
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
COBJS-y += partition.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
......
/*
* (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
*
* derived from previous work
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
......@@ -23,78 +27,44 @@
*/
#include <common.h>
#include <exports.h>
#include <netdev.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_pmc.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
int board_init(void)
{
/* Enable Ctrlc */
console_init_f ();
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/*
* Correct IRDA resistor problem
* Set PA23_TXD in Output
*/
writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER);
/*
* memory and cpu-speed are setup before relocation
* so we do _nothing_ here
*/
writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
/* arch number of AT91RM9200EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
return at91emac_register(bis, (u32) AT91_EMAC_BASE);
}
#endif
CONFIG_SYS_TEXT_BASE = 0x21f00000
# currently only NOR flash booting is supported
CONFIG_SYS_TEXT_BASE = 0x10000000
......@@ -3,6 +3,9 @@
* Atmel Nordic AB <www.atmel.com>
* Ulf Samuelsson <ulf@atmel.com>
*
* (C) Copyright 2010
* Andreas Bießmann <andreas.devel@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
......@@ -23,67 +26,62 @@
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pmc.h>
#define GREEN_LED AT91C_PIO_PB0
#define YELLOW_LED AT91C_PIO_PB1
#define RED_LED AT91C_PIO_PB2
/* bit mask in PIO port B */
#define GREEN_LED (1<<0)
#define YELLOW_LED (1<<1)
#define RED_LED (1<<2)
void green_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(GREEN_LED, PIOB->PIO_CODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(GREEN_LED, &pio->piob.codr);
}
void yellow_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(YELLOW_LED, PIOB->PIO_CODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(YELLOW_LED, &pio->piob.codr);
}
void red_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(RED_LED, PIOB->PIO_CODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(RED_LED, &pio->piob.codr);
}
void green_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(GREEN_LED, PIOB->PIO_SODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(GREEN_LED, &pio->piob.sodr);
}
void yellow_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(YELLOW_LED, PIOB->PIO_SODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(YELLOW_LED, &pio->piob.sodr);
}
void red_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(RED_LED, PIOB->PIO_SODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(RED_LED, &pio->piob.sodr);
}
void coloured_LED_init (void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
AT91PS_PMC PMC = AT91C_BASE_PMC;
at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/* Enable PIOB clock */
writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER);
writel(1 << AT91_ID_PIOB, &pmc->pcer);
/* Disable peripherals on LEDs */
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER);
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
/* Enable pins as outputs */
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER);
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
/* Turn all LEDs OFF */
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR);
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
}
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <at91rm9200_net.h>
#include <dm9161.h>
#include <net.h>
int board_late_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
/* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
eth_init(gd->bd);
return 0;
}
/* checks if addr is in RAM */
int addr2ram(ulong addr)
{
int result = 0;
if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE)))
result = 1;
return result;
}
#include <config.h>
#include <common.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <dataflash.h>
int AT91F_GetMuxStatus(void)
{
/* Set in PIO mode */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
/* Configure in output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO)
return 1;
return 0;
}
void AT91F_SelectMMC(void)
{
/* Set in PIO mode */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
/* Configure in output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
/* Set Output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_SODR);
}
void AT91F_SelectSPI(void)
{
/* Set in PIO mode */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
/* Configure in output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
/* Clear Output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_CODR);
}
/*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <asm/hardware.h>
#include <dataflash.h>
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
};
/*define the area offsets*/
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
};
......@@ -344,7 +344,7 @@ modnet50 arm arm720t
lpc2292sodimm arm arm720t - - lpc2292
eb_cpux9k2 arm arm920t - BuS at91
at91rm9200dk arm arm920t - atmel at91rm9200
at91rm9200ek arm arm920t - atmel at91rm9200
at91rm9200ek arm arm920t - atmel at91
sbc2410x arm arm920t - - s3c24x0
smdk2400 arm arm920t - samsung s3c24x0
smdk2410 arm arm920t - samsung s3c24x0
......
/*
* Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
*
* based on previous work by
*
* Ulf Samuelsson <ulf@atmel.com>
* Rick Bronson <rick@efn.org>
*
......@@ -23,40 +27,52 @@
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#ifndef __AT91RM9200EK_CONFIG_H__
#define __AT91RM9200EK_CONFIG_H__
#define CONFIG_AT91_LEGACY
#include <asm/sizes.h>
/* ARM asynchronous clock */
/*
* from 18.432 MHz crystal
* (18432000 / 4 * 39)
*/
#define AT91C_MAIN_CLOCK 179712000
/*
* peripheral clock
* (AT91C_MASTER_CLOCK / 3)
* AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
* AT91C_MAIN_CLOCK is the frequency of PLLA output
* AT91C_MASTER_CLOCK is the peripherial clock
* CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
* set in arch/arm/cpu/arm920t/at91/timer.c)
* CONFIG_SYS_HZ is the tick rate for timer tc0
*/
#define AT91C_MASTER_CLOCK 59904000
#define AT91C_XTAL_CLOCK 18432000
#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
#define CONFIG_SYS_HZ 1000
#define AT91_SLOW_CLOCK 32768 /* slow clock */
/* CPU configuration */
#define CONFIG_ARM920T
#define CONFIG_AT91RM9200
#define CONFIG_AT91RM9200EK
#define CONFIG_CPUAT91
#define USE_920T_MMU
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
#define CONFIG_AT91RM9200EK 1 /* on an AT91RM9200EK Board */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define USE_920T_MMU 1
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*
* Memory Configuration
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE SZ_32M
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END \
(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
/*
* LowLevel Init
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
#define CONFIG_SYS_USE_MAIN_OSCILLATOR
/* flash */
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
......@@ -73,50 +89,26 @@
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
#else
#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
/*
* Memory Configuration
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END \
(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144)
/*
* Hardware drivers
*/
/*
* UART Configuration
*
* define one of these to choose the DBGU,
* USART0 or USART1 as console
* Choose a USART for serial console
* CONFIG_DBGU is DBGU unit on J10
* CONFIG_USART1 is USART1 on J14
*/
#define CONFIG_AT91RM9200_USART
#define CONFIG_DBGU
#undef CONFIG_USART0
#undef CONFIG_USART1
/* don't include RTS/CTS flow control support */
#undef CONFIG_HWFLOW
/* disable modem initialization stuff */
#undef CONFIG_MODEM_SUPPORT
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_BAUDRATE 115200
......@@ -130,156 +122,60 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_LOADS
#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
/* Options for MMC/SD Card */
#define CONFIG_DOS_PARTITION 1
#undef CONFIG_MMC
#define CONFIG_SYS_MMC_BASE 0xFFFB4000
#define CONFIG_SYS_MMC_BLOCKSIZE 512
/*
* Network Driver Setting
*/
#define CONFIG_NET_MULTI 1
#ifdef CONFIG_NET_MULTI
#define CONFIG_DRIVER_AT91EMAC 1
#define CONFIG_SYS_RX_ETH_BUFFER 8
#else
#define CONFIG_DRIVER_ETHER 1
#endif
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91C_USE_RMII
/*
* AC Characteristics
* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns
*/
#define DATAFLASH_TCSS (0xC << 16)
#define DATAFLASH_TCHS (0x1 << 24)
#if defined(CONFIG_HAS_DATAFLASH)
#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
/* Logical adress for CS0 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
/* Logical adress for CS3 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000
#define CONFIG_SYS_SUPPORT_BLOCK_ERASE 1
#define CONFIG_SYS_DATAFLASH_MMC_PIO AT91C_PIO_PB22
#endif
#define CONFIG_NET_MULTI
#define CONFIG_DRIVER_AT91EMAC
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_RMII
#define CONFIG_MII
/*
* NOR Flash
*/
#define CONFIG_SYS_FLASH_BASE 0x10000000
#define PHYS_FLASH_SIZE 0x800000 /* 8MB */
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_BASE 0x10000000
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
#define PHYS_FLASH_SIZE SZ_8M
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_FLASH_PROTECTION
/*
* Environment Settings
*/
#ifdef CONFIG_ENV_IS_IN_DATAFLASH
/*
* Datasflash Environment Settings
*/
#define CONFIG_ENV_OFFSET 0x4200
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
/* 8 * 1056 really , but start.s is not OK with this*/
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH
#else
/*
* NOR Flash Environment Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
/*
* between boot.bin and u-boot.bin.gz
*/
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000)
#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
#else
/*
* after u-boot.bin
*/
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
/* The following #defines are needed to get flash environment right */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN \
(CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE)
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
#define CONFIG_SYS_MONITOR_LEN SZ_256K
/*
* Boot option
*/
#define CONFIG_BOOTDELAY 3
#ifdef CONFIG_SKIP_LOWLEVEL_INIT