Commit 9c62815b authored by Wolfgang Denk's avatar Wolfgang Denk

ARM: remove broken "modnet50" board.

Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Thomas Elste <info@elste.org>
parent d1a067a3
......@@ -133,11 +133,6 @@ N: Dave Ellis
E: DGE@sixnetio.com
D: EEPROM Speedup, SXNI855T port
N: Thomas Elste
E: info@elste.org
D: Port for the ModNET50 Board, NET+50 CPU Port
W: http://www.imms.de
N: Daniel Engstr?m
E: daniel@omicron.se
D: x86 port, Support for sc520_cdp board
......
......@@ -628,10 +628,6 @@ Wolfgang Denk <wd@denx.de>
imx27lite i.MX27
qong i.MX31
Thomas Elste <info@elste.org>
modnet50 ARM720T (NET+50)
Kristoffer Ericson <kristoffer.ericson@gmail.com>
jornada SA1110
......
......@@ -296,14 +296,6 @@ LIST_ppc=" \
LIST_SA="$(boards_by_cpu sa1100)"
#########################################################################
## ARM7 Systems
#########################################################################
LIST_ARM7=" \
modnet50 \
"
#########################################################################
## ARM9 Systems
#########################################################################
......@@ -400,7 +392,6 @@ LIST_ixp="$(boards_by_cpu ixp)
LIST_arm=" \
${LIST_SA} \
${LIST_ARM7} \
${LIST_ARM9} \
${LIST_ARM10} \
${LIST_ARM11} \
......
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := modnet50.o flash.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
#
# (C) Copyright 2000
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_SYS_TEXT_BASE = 0x00f00000
#CROSS_COMPILE = arm-elf-
This diff is collapsed.
/*
* Memory Setup stuff - taken from Linux
*
* Copyright (c) 2002 Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
* (c) 2004 IMMS gGmbH <www.imms.de>, Thomas Elste <info@elste.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/netarm_registers.h>
/* some parameters for the board */
#define FLASH_90ns_WAIT_STATES ((NETARM_PLL_COUNT_VAL + 2) / 3)
#define FLASH_70ns_WAIT_STATES 4
#define NETARM_MMAP_CS0_BASE (PHYS_FLASH_1)
#if 1
#define NETARM_MMAP_CS0_MASK (~(PHYS_FLASH_1_SIZE - 1))
#else
#define NETARM_MMAP_CS0_MASK (~(1000000 - 1))
#endif
#define NETARM_MMAP_CS1_BASE (PHYS_SDRAM_1)
#define NETARM_MMAP_CS1_MASK (~(PHYS_SDRAM_1_SIZE - 1))
#define NETARM_MMAP_CS2_BASE (PHYS_SDRAM_2)
#define NETARM_MMAP_CS2_MASK (~(PHYS_SDRAM_2_SIZE - 1))
#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
#define NETARM_MMAP_CS3_BASE (PHYS_NVRAM_1)
#define NETARM_MMAP_CS3_MASK (~(PHYS_NVRAM_SIZE - 1))
#endif
#define NETARM_MMAP_CS4_BASE (PHYS_EXT_1)
#define NETARM_MMAP_CS4_MASK (~(PHYS_EXT_SIZE - 1))
/* setting up the memory */
.globl lowlevel_init
lowlevel_init:
#if defined(CONFIG_MODNET50)
ldr pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - CONFIG_SYS_TEXT_BASE)
_jump_to_high:
/*
* MEM Config Reg
* ---------------------------------------------------
*/
ldr r0, =NETARM_MEM_MODULE_BASE
ldr r1, =( NETARM_MEM_REFR_PERIOD_USEC(16) | \
NETARM_MEM_CFG_REFRESH_EN | \
NETARM_MEM_CFG_REFR_CYCLE_5CLKS )
str r1, [r0, #+NETARM_MEM_MODULE_CONFIG]
memsetup_cs0:
/*
* Base Addr / Option Reg 0 (Flash)
* ---------------------------------------------------
*/
ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \
NETARM_MEM_BAR_DRAM_FP | \
NETARM_MEM_BAR_DRAM_MUX_INT | \
NETARM_MEM_BAR_DRAM_MUX_BAL | \
NETARM_MEM_BAR_VALID )
str r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR]
/* trust that the bus size for flash was strapped correctly */
/* this saves the bus width in r2 and then ORs it back in */
/* it's pretty safe assumption, otherwise it wouldn't boot */
ldr r2, [r0, #+NETARM_MEM_CS0_OPTIONS]
and r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK
/* just a test: assume 32 bit flash mem */
/* mov r2, #NETARM_MEM_OPT_32BIT */
ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \
NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \
NETARM_MEM_OPT_BCYC_4 | \
NETARM_MEM_OPT_BSIZE_16 | \
NETARM_MEM_OPT_16BIT | \
NETARM_MEM_OPT_READ_ASYNC | \
NETARM_MEM_OPT_WRITE_ASYNC )
orr r1, r1, r2
str r1, [r0, #+NETARM_MEM_CS0_OPTIONS]
memsetup_cs1:
/*
* Base Addr / Option Reg 1 (DRAM #1)
* ---------------------------------------------------
*/
#ifdef CONFIG_NETARM_NET40_REV2
/* we have to config SDRAM in burst mode */
ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
NETARM_MEM_OPT_BCYC_2 | \
NETARM_MEM_OPT_BSIZE_16 | \
NETARM_MEM_OPT_WAIT_STATES(0) | \
NETARM_MEM_OPT_32BIT | \
NETARM_MEM_OPT_READ_ASYNC | \
NETARM_MEM_OPT_WRITE_ASYNC )
str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
NETARM_MEM_BAR_DRAM_SYNC | \
NETARM_MEM_BAR_DRAM_MUX_INT | \
NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
NETARM_MEM_BAR_DRAM_SEL | \
NETARM_MEM_BAR_BURST_EN | \
NETARM_MEM_BAR_VALID )
str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
#else
/* we have to config FPDRAM in burst mode with smaller burst access size */
ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
NETARM_MEM_OPT_BCYC_2 | \
NETARM_MEM_OPT_BSIZE_16 | \
NETARM_MEM_OPT_WAIT_STATES(0) | \
NETARM_MEM_OPT_32BIT | \
NETARM_MEM_OPT_READ_ASYNC | \
NETARM_MEM_OPT_WRITE_ASYNC )
str r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
NETARM_MEM_BAR_DRAM_SYNC | \
NETARM_MEM_BAR_DRAM_MUX_INT | \
NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
NETARM_MEM_BAR_DRAM_SEL | \
NETARM_MEM_BAR_BURST_EN | \
NETARM_MEM_BAR_VALID )
str r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
#endif /* CONFIG_NETARM_NET40_REV2 */
memsetup_cs3:
/*
* Base Addr / Option Reg 3 (EEPROM, NVRAM)
* ---------------------------------------------------
*/
#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
ldr r1, =( NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \
NETARM_MEM_OPT_BCYC_3 | \
NETARM_MEM_OPT_BSIZE_2 | \
NETARM_MEM_OPT_WAIT_STATES(10) | \
NETARM_MEM_OPT_8BIT | \
NETARM_MEM_OPT_READ_ASYNC | \
NETARM_MEM_OPT_WRITE_ASYNC )
str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
ldr r1, =( NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \
NETARM_MEM_BAR_DRAM_FP | \
NETARM_MEM_BAR_DRAM_MUX_INT | \
NETARM_MEM_BAR_DRAM_MUX_BAL | \
NETARM_MEM_BAR_VALID )
str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
#else
/* we don't need EEPROM --> no config */
ldr r1, =( 0 )
str r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
ldr r1, =( 0 )
str r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
#endif
#else
/*
#error "missing CONFIG_MODNET50 (see your config.h)"
*/
#endif /* CONFIG_MODNET50 */
lowlevel_init_end:
/*
* manipulate address in lr and ip to match new
* address space
*/
ldr r3, =(NETARM_MMAP_CS0_BASE)
mov r0, lr
add r0, r3, r0
mov lr, r0
mov r0, ip
add r0, r3, r0
mov ip, r0
/* everything is fine now */
mov pc, lr
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
/* address for the kernel command line */
gd->bd->bi_boot_params = 0x800;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
if (CONFIG_NR_DRAM_BANKS == 2) {
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
return (0);
}
......@@ -42,7 +42,6 @@ imx31_litekit arm arm1136 - logicpd
mx35pdk arm arm1136 - freescale mx35
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
modnet50 arm arm720t
integratorap_cm720t arm arm720t integrator armltd - integratorap
integratorap_cm920t arm arm920t integrator armltd - integratorap
integratorcp_cm920t arm arm920t integrator armltd - integratorcp
......
U-BOOT Port for FSForth ModNET50 Board
--------------------------------------
author: Thomas Elste <info@elste.org>
IMMS gGmbH <www.imms.de>
The port based upon an early (partial complete)
armboot-port from Stephan Linz for the ModNET50 Board.
Overview:
- board with Netsilicon NET+50 ARM7TDMI CPU without MMU
- 16 MB SDRAM
- 2 MB Flash (MBL29LV160BE)
- 10/100 Ethernet PHY (LXT971A)
Current Configuration (include/configs/modnet50.h):
Memory Map: 0x00000000 - 0x00FFFFFF 16M SDRAM
0x10000000 - 0x101FFFFF 2M Flash
The Flash uses a BB-Architectur with 35 sectors
(0:16K; 1,2:8K; 3:32K; 4-34:64K). U-Boot is located in
the first 5 sectors.
The environment is located at the end of the 4th Flash
sector (0x1001C000-0x1001FFFF).
Build:
U-boot should be build by using the ELDK Toolchain (arm-linux-*).
make modnet50_config
make
Status:
Everything seems to work fine. Booting images was tested by
booting uCLinux (with and without a separate ramdisk image) from
flash.
Files:
arch/arm/cpu/arm720t/serial_netarm.c .. serial I/O for the cpu
board/modnet50/lowlevel_init.S .. memory setup for ModNET50
board/modnet50/flash.c .. flash routines
board/modnet50/modnet50.c .. some board init stuff
drivers/net/netarm_eth.c .. ethernet driver for the NET+50 CPU
drivers/net/netarm_eth.h .. header for ethernet driver
include/configs/modnet50.h .. configuration file for ModNET50
include/netarm_*.h .. register and macro definitions for
the NETARM CPU family
doc/README.modnet50 .. this readme
......@@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU removed Commit last known maintainer/contact
=============================================================================
modnet50 arm arm720t - 2011-09-05 Thomas Elste <info@elste.org>
lpc2292sodimm arm arm720t - 2011-09-05
lart arm sa1100 - 2011-09-05 Alex Züpke <azu@sysgo.de>
impa7 arm arm720t - 2011-09-05 Marius Gröger <mag@sysgo.de>
......
/*
* (C) Copyright 2004
* IMMS, gGmbH <www.imms.de>
* Thomas Elste <info@elste.org>
*
* Configuation settings for ModNET50 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
#define CONFIG_NETARM /* it's a Netsiclicon NET+ARM */
#undef CONFIG_NETARM_NET40_REV2 /* it's a Net+40 Rev. 2 */
#undef CONFIG_NETARM_NET40_REV4 /* it's a Net+40 Rev. 4 */
#define CONFIG_NETARM_NET50 /* it's a Net+50 */
#define CONFIG_MODNET50 1 /* on an ModNET50 Board */
#undef CONFIG_USE_IRQ /* don't need them anymore */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
#define CONFIG_DRIVER_NETARMETH 1
/*
* select serial console configuration
*/
#define CONFIG_NETARM_SERIAL
#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 38400
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_JFFS2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.30.2
#define CONFIG_SERVERIP 192.168.30.122
#define CONFIG_SYS_ETH_PHY_ADDR 0x100
#define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */
/*#define CONFIG_BOOTDELAY 10*/
/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */
#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000"
#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K " \
"root=/dev/ram keepinitrd"
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "modnet50 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00500000 /* default load address */
#define CONFIG_SYS_HZ 900 /* decrementer freq: 2 kHz */
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
#define PHYS_SDRAM_2 0x01000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */
#define PHYS_FLASH_1 0x10000000 /* Flash Bank #1 */
#define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip only, 16bit access) */
#define PHYS_FLASH_2 0x10200001
#define PHYS_FLASH_2_SIZE 0x00200000
#define CONFIG_NETARM_EEPROM
/* #ifdef CONFIG_NETARM_EEPROM */
#define PHYS_NVRAM_1 0x20000000 /* EEPROM Bank #1 */
#define PHYS_NVRAM_SIZE 0x00002000 /* 8 KB */
/* #endif */
#define PHYS_EXT_1 0x30000000 /* Extensions Bank #1 */
#define PHYS_EXT_SIZE 0x01000000 /* 32 MB memory mapped I/O */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_1_SIZE
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
#define CONFIG_SYS_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
/* environment settings */
#define CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_ADDR 0x1001C000 /* environment start address */
#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE 0x4000 /* max size for environment */
/*
* JFFS2 partitions
*
*/
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET 0x00080000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nor0=modnet50-0"
#define MTDPARTS_DEFAULT "mtdparts=modnet50-0:-@512k(jffs2)"
*/
#endif /* __CONFIG_H */
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