Commit 9f64ba24 authored by Mike Frysinger's avatar Mike Frysinger
Browse files

Blackfin: bf533-stamp: bump up default clocks



Since the hardware can handle it, bump the default clocks from 80mhz SCLK
and 398mhz CCLK to 100mhz SCLK and 498mhz CCLK.
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 23fd959e
......@@ -30,7 +30,7 @@
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 36
#define CONFIG_VCO_MULT 45
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
......
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