Commit a19d1625 authored by Angus Ainslie (Purism)'s avatar Angus Ainslie (Purism)
Browse files

board: purism: librem5: add the phone support files


Signed-off-by: default avatarAngus Ainslie (Purism) <angus@akkea.ca>
parent ed2b820a
......@@ -627,6 +627,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
fsl-imx8mq-ddr3l-arm2.dtb \
fsl-imx8mq-ddr4-arm2.dtb \
fsl-imx8mm-evk.dtb \
librem5.dtb \
librem5-devkit.dtb \
fsl-imx8mm-ddr3l-val.dtb \
fsl-imx8mm-ddr4-evk.dtb \
......
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright (C) 2018 EmCraft Systems
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "fsl-imx8mq.dtsi"
/ {
model = "Librem 5";
compatible = "purism,librem5", "fsl,imx8mq";
chosen {
bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
stdout-path = &uart1;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
pwmleds {
compatible = "pwm-leds";
ledpwm2 {
label = "PWM2";
pwms = <&pwm2 0 50000>;
max-brightness = <255>;
};
};
};
&iomuxc {
pinctrl-names = "default";
imx8m-som {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000003f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000003f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000003f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000003f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000003f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000003f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000003f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000003f
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 /* MOTO */
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 /* LED_B */
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16 /* LED_R */
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16 /* LED_G */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcf
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8f
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WIFI_nRST */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&lcdif {
status = "okay";
disp-dev = "mipi_dsi_northwest";
display = <&display0>;
display0: display@0 {
bits-per-pixel = <24>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <8>;
hback-porch = <4>;
hsync-len = <41>;
vback-porch = <2>;
vfront-porch = <4>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&uart3 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
fsl,uart-has-rtscts;
status = "disabled";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
//vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
status = "okay";
dr_mode = "peripheral";
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
......@@ -497,6 +497,46 @@ struct bootrom_sw_info {
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
/* ECSPI registers */
struct cspi_regs {
u32 rxdata;
u32 txdata;
u32 ctrl;
u32 cfg;
u32 intr;
u32 dma;
u32 stat;
u32 period;
};
/*
* CSPI register definitions
*/
#define MXC_ECSPI
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
#define MXC_CSPICTRL_MAXBITS 0xfff
#define MXC_CSPICTRL_TC (1 << 7)
#define MXC_CSPICTRL_RXOVF (1 << 6)
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
#define MAX_SPI_BYTES 32
/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
#define MXC_CSPICON_PHA 0 /* SCLK phase control */
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#include <stdbool.h>
bool is_usb_boot(void);
#define is_boot_from_usb is_usb_boot
......
......@@ -57,6 +57,11 @@ config TARGET_IMX8MM_DDR4_EVK
select IMX8MM
select IMX8M_DDR4
config TARGET_LIBREM5
bool "Purism Librem5 Phone"
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_LIBREM5_DEVKIT
bool "Purism Librem5 devkit board"
select IMX8MQ
......@@ -67,6 +72,7 @@ source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mq_arm2/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mm_val/Kconfig"
source "board/purism/librem5/Kconfig"
source "board/purism/librem5_devkit/Kconfig"
endif
if TARGET_LIBREM5
config SYS_BOARD
default "librem5"
config SYS_VENDOR
default "purism"
config SYS_CONFIG_NAME
default "librem5"
source "board/purism/common/Kconfig"
endif
i.MX8MQ EVK BOARD
M: Peng Fan <peng.fan@nxp.com>
M: Fabio Estevam <festevam@gmail.com>
S: Maintained
F: board/freescale/imx8mq_evk/
F: include/configs/imx8mq_evk.h
F: configs/imx8mq_evk_defconfig
#
# Copyright 2017 NXP
# Copyright 2019 Purism
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += librem5.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
endif
U-Boot for the NXP i.MX8MQ EVK board
Quick Start
===========
- Build the ARM Trusted firmware binary
- Get ddr and hdmi fimware
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
======================================
Note: srctree is U-Boot source directory
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
branch: imx_4.14.62_1.0.0_beta
$ make PLAT=imx8mq bl31
$ cp build/imx8mq/release/bl31.bin $(srctree)
Get the ddr and hdmi firmware
=============================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
$ chmod +x firmware-imx-7.9.bin
$ ./firmware-imx-7.9.bin
$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree)
$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Build U-Boot
============
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx8mq_evk_defconfig
$ make flash.bin
Burn the flash.bin to MicroSD card offset 33KB
$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
Boot
====
Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2019 Purism
*/
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm-generic/gpio.h>
#include <fsl_esdhc.h>
#include <mmc.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/video.h>
#include <asm/arch/video_common.h>
#include <spl.h>
#include <power/pmic.h>
#include "../common/tcpc.h"
#include <usb.h>
#include <dwc3-uboot.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
return 0;
}
#endif
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
/* TODO */
return 0;
}
#endif
int dram_init(void)
{
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
else
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
#ifdef CONFIG_USB_DWC3
#define USB_PHY_CTRL0 0xF0040
#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
#define USB_PHY_CTRL1 0xF0044
#define USB_PHY_CTRL1_RESET BIT(0)
#define USB_PHY_CTRL1_COMMONONN BIT(1)
#define USB_PHY_CTRL1_ATERESET BIT(3)
#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
#define USB_PHY_CTRL2 0xF0048
#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
static struct dwc3_device dwc3_device_data = {
#ifdef CONFIG_SPL_BUILD
.maximum_speed = USB_SPEED_HIGH,
#else
.maximum_speed = USB_SPEED_SUPER,
#endif
.base = USB1_BASE_ADDR,
.dr_mode = USB_DR_MODE_PERIPHERAL,
.index = 0,
.power_down_scale = 2,
};
int usb_gadget_handle_interrupts(void)