Commit a1b215e2 authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Merge branch 'master' of git://www.denx.de/git/u-boot-at91

parents f9eabcb3 b5873f17
......@@ -530,6 +530,11 @@ Dave Peverley <dpeverley@mpc-data.co.uk>
omap730p2 ARM926EJS
Stelian Pop <stelian.pop@leadtechdesign.com>
at91cap9adk ARM926EJS (AT91CAP9 SoC)
at91sam9260ek ARM926EJS (AT91SAM9260 SoC)
Stefan Roese <sr@denx.de>
ixdpg425 xscale
......
......@@ -452,6 +452,7 @@ LIST_ARM7=" \
LIST_ARM9=" \
at91cap9adk \
at91rm9200dk \
at91sam9260ek \
cmc_pu2 \
ap920t \
ap922_XA10 \
......@@ -463,6 +464,8 @@ LIST_ARM9=" \
cp926ejs \
cp946es \
cp966 \
csb637 \
kb9202 \
lpd7a400 \
m501sk \
mp2usb \
......@@ -472,6 +475,7 @@ LIST_ARM9=" \
omap1510inn \
omap1610h2 \
omap1610inn \
omap5912osk \
omap730p2 \
sbc2410x \
scb9328 \
......
......@@ -2308,11 +2308,14 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
at91cap9adk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91cap9
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91sam9
at91rm9200dk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
at91sam9260ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9
cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
......
......@@ -25,10 +25,12 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := at91cap9adk.o led.o nand.o
COBJS-y += at91cap9adk.o
COBJS-y += led.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
......
......@@ -23,7 +23,13 @@
*/
#include <common.h>
#include <asm/arch/AT91CAP9.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91cap9_matrix.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
......@@ -40,126 +46,106 @@ DECLARE_GLOBAL_DATA_PTR;
static void at91cap9_serial_hw_init(void)
{
#ifdef CONFIG_USART0
AT91C_BASE_PIOA->PIO_PDR = AT91C_PA22_TXD0 | AT91C_PA23_RXD0;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US1;
at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
AT91C_BASE_PIOD->PIO_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US2;
at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */
AT91C_BASE_PIOC->PIO_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
#endif
}
static void at91cap9_nor_hw_init(void)
{
/* Ensure EBI supply is 3.3V */
AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_SUP_3V3;
unsigned long csa;
/* Ensure EBI supply is 3.3V */
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
/* Configure SMC CS0 for parallel flash */
AT91C_BASE_SMC->SMC_SETUP0 = AT91C_FLASH_NWE_SETUP |
AT91C_FLASH_NCS_WR_SETUP |
AT91C_FLASH_NRD_SETUP |
AT91C_FLASH_NCS_RD_SETUP;
AT91C_BASE_SMC->SMC_PULSE0 = AT91C_FLASH_NWE_PULSE |
AT91C_FLASH_NCS_WR_PULSE |
AT91C_FLASH_NRD_PULSE |
AT91C_FLASH_NCS_RD_PULSE;
AT91C_BASE_SMC->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE |
AT91C_FLASH_NRD_CYCLE;
AT91C_BASE_SMC->SMC_CTRL0 = AT91C_SMC_READMODE |
AT91C_SMC_WRITEMODE |
AT91C_SMC_NWAITM_NWAIT_DISABLE |
AT91C_SMC_BAT_BYTE_WRITE |
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
(AT91C_SMC_TDF & (1 << 16));
at91_sys_write(AT91_SMC_SETUP(0),
AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
at91_sys_write(AT91_SMC_PULSE(0),
AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
at91_sys_write(AT91_SMC_CYCLE(0),
AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
at91_sys_write(AT91_SMC_MODE(0),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
}
#ifdef CONFIG_CMD_NAND
static void at91cap9_nand_hw_init(void)
{
unsigned long csa;
/* Enable CS3 */
AT91C_BASE_CCFG->CCFG_EBICSA |= AT91C_EBI_CS3A_SM | AT91C_EBI_SUP_3V3;
csa = at91_sys_read(AT91_MATRIX_EBICSA);
at91_sys_write(AT91_MATRIX_EBICSA,
csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
/* Configure SMC CS3 for NAND/SmartMedia */
AT91C_BASE_SMC->SMC_SETUP3 = AT91C_SM_NWE_SETUP |
AT91C_SM_NCS_WR_SETUP |
AT91C_SM_NRD_SETUP |
AT91C_SM_NCS_RD_SETUP;
AT91C_BASE_SMC->SMC_PULSE3 = AT91C_SM_NWE_PULSE |
AT91C_SM_NCS_WR_PULSE |
AT91C_SM_NRD_PULSE |
AT91C_SM_NCS_RD_PULSE;
AT91C_BASE_SMC->SMC_CYCLE3 = AT91C_SM_NWE_CYCLE |
AT91C_SM_NRD_CYCLE;
AT91C_BASE_SMC->SMC_CTRL3 = AT91C_SMC_READMODE |
AT91C_SMC_WRITEMODE |
AT91C_SMC_NWAITM_NWAIT_DISABLE |
AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
AT91C_SM_TDF;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
at91_sys_write(AT91_SMC_SETUP(3),
AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
at91_sys_write(AT91_SMC_PULSE(3),
AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
at91_sys_write(AT91_SMC_CYCLE(3),
AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
at91_sys_write(AT91_SMC_MODE(3),
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_DBW_8 | AT91_SMC_TDF_(1));
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
/* RDY/BSY is not connected */
/* Enable NandFlash */
AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15;
AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15;
at91_set_gpio_output(AT91_PIN_PD15, 1);
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
static void at91cap9_spi_hw_init(void)
{
AT91C_BASE_PIOD->PIO_BSR = AT91C_PD0_SPI0_NPCS2D |
AT91C_PD1_SPI0_NPCS3D;
AT91C_BASE_PIOD->PIO_PDR = AT91C_PD0_SPI0_NPCS2D |
AT91C_PD1_SPI0_NPCS3D;
AT91C_BASE_PIOA->PIO_ASR = AT91C_PA28_SPI0_NPCS3A;
AT91C_BASE_PIOA->PIO_BSR = AT91C_PA4_SPI0_NPCS2A |
AT91C_PA1_SPI0_MOSI |
AT91C_PA0_SPI0_MISO |
AT91C_PA3_SPI0_NPCS1 |
AT91C_PA5_SPI0_NPCS0 |
AT91C_PA2_SPI0_SPCK;
AT91C_BASE_PIOA->PIO_PDR = AT91C_PA28_SPI0_NPCS3A |
AT91C_PA4_SPI0_NPCS2A |
AT91C_PA1_SPI0_MOSI |
AT91C_PA0_SPI0_MISO |
AT91C_PA3_SPI0_NPCS1 |
AT91C_PA5_SPI0_NPCS0 |
AT91C_PA2_SPI0_SPCK;
/* Enable Clock */
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI0;
at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
}
#endif
#ifdef CONFIG_MACB
static void at91cap9_macb_hw_init(void)
{
unsigned int gpio;
/* Enable clock */
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC);
/*
* Disable pull-up on:
......@@ -169,54 +155,59 @@ static void at91cap9_macb_hw_init(void)
*
* PHY has internal pull-down
*/
AT91C_BASE_PIOB->PIO_PPUDR = AT91C_PB22_E_RXDV |
AT91C_PB25_E_RX0 |
AT91C_PB26_E_RX1;
writel(pin_to_mask(AT91_PIN_PB22) |
pin_to_mask(AT91_PIN_PB25) |
pin_to_mask(AT91_PIN_PB26),
pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
/* Need to reset PHY -> 500ms reset */
AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
(AT91C_RSTC_ERSTL & (0x0D << 8)) |
AT91C_RSTC_URSTEN;
AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & (0xA5 << 24)) |
AT91C_RSTC_EXTRST;
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
AT91_RSTC_ERSTL | (0x0D << 8) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL));
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Re-enable pull-up */
AT91C_BASE_PIOB->PIO_PPUER = AT91C_PB22_E_RXDV |
AT91C_PB25_E_RX0 |
AT91C_PB26_E_RX1;
#ifdef CONFIG_RMII
gpio = AT91C_PB30_E_MDIO |
AT91C_PB29_E_MDC |
AT91C_PB21_E_TXCK |
AT91C_PB27_E_RXER |
AT91C_PB25_E_RX0 |
AT91C_PB22_E_RXDV |
AT91C_PB26_E_RX1 |
AT91C_PB28_E_TXEN |
AT91C_PB23_E_TX0 |
AT91C_PB24_E_TX1;
AT91C_BASE_PIOB->PIO_ASR = gpio;
AT91C_BASE_PIOB->PIO_BSR = 0;
AT91C_BASE_PIOB->PIO_PDR = gpio;
#else
#error AT91CAP9A-DK works only in RMII mode
writel(pin_to_mask(AT91_PIN_PB22) |
pin_to_mask(AT91_PIN_PB25) |
pin_to_mask(AT91_PIN_PB26),
pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
#ifndef CONFIG_RMII
at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
#endif
/* Unlock EMAC, 3 0 2 1 sequence */
#define MP_MAC_KEY0 0x5969cb2a
#define MP_MAC_KEY1 0xb4a1872e
#define MP_MAC_KEY2 0x05683fbc
#define MP_MAC_KEY3 0x3634fba4
#define UNLOCK_MAC 0x00000008
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_MAC_KEY3;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_MAC_KEY0;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_MAC_KEY2;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_MAC_KEY1;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_MAC;
writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c);
writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30);
writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38);
writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34);
writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40);
}
#endif
......@@ -229,11 +220,11 @@ static void at91cap9_uhp_hw_init(void)
#define MP_OHCI_KEY2 0x4823efbc
#define MP_OHCI_KEY3 0x8651aae4
#define UNLOCK_OHCI 0x00000010
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x3c)) = MP_OHCI_KEY3;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x38)) = MP_OHCI_KEY2;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x30)) = MP_OHCI_KEY0;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x34)) = MP_OHCI_KEY1;
*((AT91_REG *)((AT91_REG) MP_BLOCK_3_BASE + 0x40)) = UNLOCK_OHCI;
writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c);
writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38);
writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30);
writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34);
writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40);
}
#endif
......
......@@ -23,58 +23,55 @@
*/
#include <common.h>
#include <asm/arch/AT91CAP9.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#define RED_LED AT91C_PIO_PC29 /* this is the power led */
#define GREEN_LED AT91C_PIO_PA10 /* this is the user1 led */
#define YELLOW_LED AT91C_PIO_PA11 /* this is the user1 led */
#define RED_LED AT91_PIN_PC29 /* this is the power led */
#define GREEN_LED AT91_PIN_PA10 /* this is the user1 led */
#define YELLOW_LED AT91_PIN_PA11 /* this is the user1 led */
void red_LED_on(void)
{
AT91C_BASE_PIOC->PIO_SODR = RED_LED;
at91_set_gpio_value(RED_LED, 1);
}
void red_LED_off(void)
{
AT91C_BASE_PIOC->PIO_CODR = RED_LED;
at91_set_gpio_value(RED_LED, 0);
}
void green_LED_on(void)
{
AT91C_BASE_PIOA->PIO_CODR = GREEN_LED;
at91_set_gpio_value(GREEN_LED, 0);
}
void green_LED_off(void)
{
AT91C_BASE_PIOA->PIO_SODR = GREEN_LED;
at91_set_gpio_value(GREEN_LED, 1);
}
void yellow_LED_on(void)
{
AT91C_BASE_PIOA->PIO_CODR = YELLOW_LED;
at91_set_gpio_value(YELLOW_LED, 0);
}
void yellow_LED_off(void)
{
AT91C_BASE_PIOA->PIO_SODR = YELLOW_LED;
at91_set_gpio_value(YELLOW_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD;
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);
/* Disable peripherals on LEDs */
AT91C_BASE_PIOA->PIO_PER = GREEN_LED | YELLOW_LED;
/* Enable pins as outputs */
AT91C_BASE_PIOA->PIO_OER = GREEN_LED | YELLOW_LED;
/* Turn all LEDs OFF */
AT91C_BASE_PIOA->PIO_SODR = GREEN_LED | YELLOW_LED;
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
/* Disable peripherals on LEDs */
AT91C_BASE_PIOC->PIO_PER = RED_LED;
/* Enable pins as outputs */
AT91C_BASE_PIOC->PIO_OER = RED_LED;
/* Turn all LEDs OFF */
AT91C_BASE_PIOC->PIO_CODR = RED_LED;
at91_set_gpio_output(RED_LED, 0);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_output(YELLOW_LED, 1);
}
......@@ -25,9 +25,9 @@
*/
#include <common.h>
#include <asm/arch/hardware.h>
#ifdef CONFIG_CMD_NAND
#include <asm/arch/at91cap9.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
......@@ -51,10 +51,10 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
AT91C_BASE_PIOD->PIO_SODR = AT91C_PIO_PD15;
at91_set_gpio_value(AT91_PIN_PD15, 1);
break;
case NAND_CTL_SETNCE:
AT91C_BASE_PIOD->PIO_CODR = AT91C_PIO_PD15;
at91_set_gpio_value(AT91_PIN_PD15, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
......@@ -68,4 +68,3 @@ int board_nand_init(struct nand_chip *nand)
return 0;
}
#endif
#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += at91sam9260ek.o
COBJS-y += led.o
COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian.pop <at> leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam926x_mc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
static void at91sam9260ek_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
#endif
#ifdef CONFIG_USART1
at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
#endif
#ifdef CONFIG_USART2
at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
#endif
#ifdef CONFIG_USART3 /* DBGU */