Commit a21d0c2c authored by TsiChung Liew's avatar TsiChung Liew Committed by John Rigby
Browse files

ColdFire: Add SBF support for M52277EVB



Add serial boot support
Signed-off-by: default avatarTsiChung Liew <Tsi-Chung.Liew@freescale.com>
parent b202816c
......@@ -1932,7 +1932,27 @@ ZPC1900_config: unconfig
## Coldfire
#########################################################################
M52277EVB_config: unconfig
M52277EVB_config \
M52277EVB_spansion_config \
M52277EVB_stmicro_config : unconfig
@case "$@" in \
M52277EVB_config) FLASH=SPANSION;; \
M52277EVB_spansion_config) FLASH=SPANSION;; \
M52277EVB_stmicro_config) FLASH=STMICRO;; \
esac; \
if [ "$${FLASH}" = "SPANSION" ] ; then \
echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
$(XECHO) "... with SPANSION boot..." ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
cp $(obj)board/freescale/m52277evb/u-boot.stm $(obj)board/freescale/m52277evb/u-boot.lds ; \
$(XECHO) "... with ST Micro boot..." ; \
fi
@$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale
M5235EVB_config \
......
......@@ -22,4 +22,6 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
......@@ -38,8 +38,18 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
u32 dramsize;
#ifdef CONFIG_CF_SBF
/*
* Serial Boot: The dram is already initialized in start.S
* only require to return DRAM size
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
u32 dramsize, i;
volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
......@@ -49,6 +59,8 @@ phys_size_t initdram(int board_type)
}
i--;
gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
......@@ -56,24 +68,30 @@ phys_size_t initdram(int board_type)
/* Issue PALL */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
__asm__("nop");
/* Issue LEMR */
/*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */
sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
__asm__("nop");
sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
__asm__("nop");
udelay(1000);
/* Issue PALL */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
__asm__("nop");
/* Perform two refresh cycles */
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
__asm__("nop");
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
udelay(100);
#endif
return (dramsize);
};
......
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf5227x/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
*(.got)
__got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
_end = . ;
PROVIDE (end = .);
}
......@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o
COBJS = cpu.o speed.o cpu_init.o interrupts.o dspi.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
......
......@@ -45,6 +45,7 @@ void cpu_init_f(void)
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
#if !defined(CONFIG_CF_SBF)
/* Workaround, must place before fbcs */
pll->psr = 0x12;
......@@ -58,37 +59,44 @@ void cpu_init_f(void)
scm1->pacrg = 0;
scm1->pacri = 0;
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
fbcs->csar0 = CONFIG_SYS_CS0_BASE;
fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#endif /* CONFIG_CF_SBF */
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
fbcs->csar1 = CONFIG_SYS_CS1_BASE;
fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
fbcs->csar2 = CONFIG_SYS_CS2_BASE;
fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
fbcs->csar3 = CONFIG_SYS_CS3_BASE;
fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
fbcs->csar4 = CONFIG_SYS_CS4_BASE;
fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
&& defined(CONFIG_SYS_CS5_CTRL))
fbcs->csar5 = CONFIG_SYS_CS5_BASE;
fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
......
/*
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <spi.h>
#include <malloc.h>
#if defined(CONFIG_CF_DSPI)
#include <asm/immap.h>
void dspi_init(void)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio->par_dspi =
GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK;
dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
#ifdef CONFIG_SYS_DSPI_DCTAR0
dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR1
dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR2
dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR3
dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR4
dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR5
dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR6
dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
#endif
#ifdef CONFIG_SYS_DSPI_DCTAR7
dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
#endif
}
void dspi_tx(int chipsel, u8 attrib, u16 data)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
while ((dspi->dsr & 0x0000F000) >= 4) ;
dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
}
u16 dspi_rx(void)
{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
while ((dspi->dsr & 0x000000F0) == 0) ;
return (dspi->drfr & 0xFFFF);
}
#if defined(CONFIG_CMD_SPI)
void spi_init_f(void)
{
}
void spi_init_r(void)
{
}
void spi_init(void)
{
dspi_init();
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct spi_slave *slave;
slave = malloc(sizeof(struct spi_slave));
if (!slave)
return NULL;
switch (cs) {
case 0:
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
break;
case 2:
gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
break;
}
slave->bus = bus;
slave->cs = cs;
return slave;
}
void spi_free_slave(struct spi_slave *slave)
{
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
switch (slave->cs) {
case 0:
gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
break;
case 2:
gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
break;
}
free(slave);
}
int spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
static int bWrite = 0;
u8 *spi_rd, *spi_wr;
int len = bitlen >> 3;
spi_rd = (u8 *) din;
spi_wr = (u8 *) dout;
/* command handling */
if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
switch (*spi_wr) {
case 0x02: /* Page Prog */
bWrite = 1;
dspi_tx(slave->cs, 0x80, spi_wr[0]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[1]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[2]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[3]);
dspi_rx();
return 0;
case 0x05: /* Read Status */
if (len == 4)
if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
&& (spi_wr[3] == 0xFF)) {
dspi_tx(slave->cs, 0x80, *spi_wr);
dspi_rx();
}
return 0;
case 0x06: /* WREN */
dspi_tx(slave->cs, 0x00, *spi_wr);
dspi_rx();
return 0;
case 0x0B: /* Fast read */
if ((len == 5) && (spi_wr[4] == 0)) {
dspi_tx(slave->cs, 0x80, spi_wr[0]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[1]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[2]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[3]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[4]);
dspi_rx();
}
return 0;
case 0x9F: /* RDID */
dspi_tx(slave->cs, 0x80, *spi_wr);
dspi_rx();
return 0;
case 0xD8: /* Sector erase */
if (len == 4)
if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
dspi_tx(slave->cs, 0x80, spi_wr[0]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[1]);
dspi_rx();
dspi_tx(slave->cs, 0x80, spi_wr[2]);
dspi_rx();
dspi_tx(slave->cs, 0x00, spi_wr[3]);
dspi_rx();
}
return 0;
}
}
if (bWrite)
len--;
while (len--) {
if (dout != NULL) {
dspi_tx(slave->cs, 0x80, *spi_wr);
dspi_rx();
spi_wr++;
}
if (din != NULL) {
dspi_tx(slave->cs, 0x80, 0);
*spi_rd = dspi_rx();
spi_rd++;
}
}
if (flags == SPI_XFER_END) {
if (bWrite) {
dspi_tx(slave->cs, 0x00, *spi_wr);
dspi_rx();
bWrite = 0;
} else {
dspi_tx(slave->cs, 0x00, 0);
dspi_rx();
}
}
return 0;
}
#endif /* CONFIG_CMD_SPI */
#endif /* CONFIG_CF_DSPI */
......@@ -90,17 +90,33 @@ int get_clocks(void)
int vco, temp, pcrvalue, pfdr;
u8 bootmode;
bootmode = (ccm->ccr & 0x000C) >> 2;
pcrvalue = pll->pcr & 0xFF0F0FFF;
pfdr = pcrvalue >> 24;
if (pfdr != 0x1E) {
if (pfdr == 0x1E)
bootmode = 0; /* Normal Mode */
#ifdef CONFIG_CF_SBF
bootmode = 3; /* Serial Mode */
#endif
if (bootmode == 0) {
/* Normal mode */
vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
/* Default value */
pcrvalue = (pll->pcr & 0x00FFFFFF);
pcrvalue |= 0x1E << 24;
pll->pcr = pcrvalue;
vco =
((pll->pcr & 0xFF000000) >> 24) *
CONFIG_SYS_INPUT_CLKSRC;
}
gd->vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
} else {
/* Normal Mode */
vco = pfdr * CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco;
vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco; /* Vco clock */
}
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
......
......@@ -46,6 +46,11 @@
addl #60,%sp; /* space for 15 regs */ \
rte;
#if defined(CONFIG_CF_SBF)
#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
.text
/*
* Vector table. This is used for initial platform startup.
......@@ -53,8 +58,14 @@
*/
_vectors:
INITSP: .long 0x00000000 /* Initial SP */
INITPC: .long _START /* Initial PC */
#if defined(CONFIG_CF_SBF)