Commit a22bba81 authored by Jagan Teki's avatar Jagan Teki

spi: zynq_spi: Fix to configure CPOL, CPHA mask

priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.
Signed-off-by: default avatarJagan Teki <jteki@openedev.com>
parent d5f60737
......@@ -272,7 +272,8 @@ static int zynq_spi_set_speed(struct udevice *bus, uint speed)
writel(confr, &regs->cr);
priv->freq = speed;
debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq);
debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
priv->regs, priv->freq);
return 0;
}
......@@ -287,9 +288,9 @@ static int zynq_spi_set_mode(struct udevice *bus, uint mode)
confr = readl(&regs->cr);
confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
if (priv->mode & SPI_CPHA)
if (mode & SPI_CPHA)
confr |= ZYNQ_SPI_CR_CPHA_MASK;
if (priv->mode & SPI_CPOL)
if (mode & SPI_CPOL)
confr |= ZYNQ_SPI_CR_CPOL_MASK;
writel(confr, &regs->cr);
......
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