Commit a420dfe2 authored by Andreas Bießmann's avatar Andreas Bießmann
Browse files

avr32: add atngw100mkii board



This patch is derived from an older patch provided by atmel in its
buildroot-avr32-v3.0.0.tar.bz2
Signed-off-by: default avatarAndreas Bießmann <andreas.devel@googlemail.com>
cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: default avatarHans-Christian Egtvedt <egtvedt@samfundet.no>
parent 93691842
......@@ -1112,6 +1112,7 @@ Wolfgang Wegner <w.wegner@astro-kom.de>
Andreas Bießmann <andreas.devel@googlemail.com>
grasshopper AT32AP7000
atngw100mkii AT32AP7000
Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
......
#
# Copyright (C) 2005-2006 Atmel Corporation
#
# See file CREDITS for list of people who contributed to this project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB := $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* Copyright (C) 2010 Atmel Corporation
*
* Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <spi.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
/* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
/* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
.virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
.phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
/* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
.col_bits = 10,
.bank_bits = 2,
.cas = 3,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 5,
.txsr = 6,
/* 7.81 us */
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
};
int board_early_init_f(void)
{
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
| HMATRIX_BIT(EBI_NAND_ENABLE));
portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
PORTMUX_DRIVE_HIGH);
portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
| PORTMUX_DRIVE_MIN);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
#if defined(CONFIG_ATMEL_SPI)
portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;
void *sdram_base;
sdram_base = uncached(EBI_SDRAM_BASE);
expected_size = sdram_init(sdram_base, &sdram_config);
actual_size = get_ram_size(sdram_base, expected_size);
if (expected_size != actual_size)
printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
actual_size >> 20, expected_size >> 20);
return actual_size;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
gd->bd->bi_phy_id[1] = 0x03;
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bi)
{
macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
return 0;
}
#endif
/* SPI chip select control */
#ifdef CONFIG_ATMEL_SPI
#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
}
#endif /* CONFIG_ATMEL_SPI */
......@@ -302,6 +302,7 @@ tec arm armv7:arm720t tec avionic
paz00 arm armv7:arm720t paz00 compal tegra20
trimslice arm armv7:arm720t trimslice compulab tegra20
atngw100 avr32 at32ap - atmel at32ap700x
atngw100mkii avr32 at32ap - atmel at32ap700x
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
atstk1004 avr32 at32ap atstk1000 atmel at32ap700x
......
/*
* Copyright (C) 2006 Atmel Corporation
*
* Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
*
* Configuration settings for the AVR32 Network Gateway
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/hardware.h>
#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100MKII
/*
* Timer clock frequency. We're using the CPU-internal COUNT register
* for this, so this is equivalent to the CPU core clock frequency
*/
#define CONFIG_SYS_HZ 1000
/*
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
* and the PBA bus to run at 1/4 the PLL frequency.
*/
#define CONFIG_PLL
#define CONFIG_SYS_POWER_MANAGER
#define CONFIG_SYS_OSC0_HZ 20000000
#define CONFIG_SYS_PLL0_DIV 1
#define CONFIG_SYS_PLL0_MUL 7
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
/*
* Set the CPU running at:
* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
*/
#define CONFIG_SYS_CLKDIV_CPU 0
/*
* Set the HSB running at:
* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
*/
#define CONFIG_SYS_CLKDIV_HSB 1
/*
* Set the PBA running at:
* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
*/
#define CONFIG_SYS_CLKDIV_PBA 2
/*
* Set the PBB running at:
* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
*/
#define CONFIG_SYS_CLKDIV_PBB 1
/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
#define CONFIG_SYS_NR_VM_REGIONS 3
/*
* The PLLOPT register controls the PLL like this:
* icp = PLLOPT<2>
* ivco = PLLOPT<1:0>
*
* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
*/
#define CONFIG_SYS_PLL0_OPT 0x04
#define CONFIG_USART_BASE ATMEL_BASE_USART1
#define CONFIG_USART_ID 1
/* User serviceable stuff */
#define CONFIG_DOS_PARTITION
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_STACKSIZE (2048)
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS \
"root=mtd:main rootfstype=jffs2"
#define CONFIG_BOOTCOMMAND \
"fsload 0x10400000 /uImage; bootm"
/*
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
* data on the serial line may interrupt the boot sequence.
*/
#define CONFIG_BOOTDELAY 1
#define CONFIG_AUTOBOOT
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT \
"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
* After booting the board for the first time, new ethernet addresses
* should be generated and assigned to the environment variables
* "ethaddr" and "eth1addr". This is normally done during production.
*/
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_NET_MULTI
/*
* BOOTP/DHCP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_MII
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_PORTMUX_PIO
#define CONFIG_SYS_NR_PIOS 5
#define CONFIG_SYS_HSDRAMC
#define CONFIG_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
#define CONFIG_ATMEL_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SYS_DCACHE_LINESZ 32
#define CONFIG_SYS_ICACHE_LINESZ 32
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE 0x00000000
#define CONFIG_SYS_FLASH_SIZE 0x800000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 65536
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
#define CONFIG_SYS_MALLOC_LEN (256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif /* __CONFIG_H */
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