Commit a56bd922 authored by wdenk's avatar wdenk

* Patch by Dave Peverley, 30 Apr 2004:

  Add support for OMAP730 Perseus2 Development board

* Patch by Alan J. Luse, 29 Apr 2004:
  Fix flash chip-select (OR0) option register setting on FADS boards.

* Patch by Alan J. Luse, 29 Apr 2004:
  Report MII network speed and duplex setting properly when
  auto-negotiate is not enabled.

* Patch by Jarrett Redd, 29 Apr 2004:
  Fix hang on reset on Ocotea board due to flash in wrong mode.
parent 5ca26799
......@@ -2,6 +2,19 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Dave Peverley, 30 Apr 2004:
Add support for OMAP730 Perseus2 Development board
* Patch by Alan J. Luse, 29 Apr 2004:
Fix flash chip-select (OR0) option register setting on FADS boards.
* Patch by Alan J. Luse, 29 Apr 2004:
Report MII network speed and duplex setting properly when
auto-negotiate is not enabled.
* Patch by Jarrett Redd, 29 Apr 2004:
Fix hang on reset on Ocotea board due to flash in wrong mode.
* Patch by Dave Peverley, 29 Apr 2004:
add MAC address detection to smc91111 driver
......
......@@ -285,6 +285,11 @@ D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
D: Support for PIP405 board
D: Support for MIP405 board
N: Dave Peverley
E: dpeverley@mpc-data.co.uk
W: http://www.mpc-data.co.uk
D: OMAP730 P2 board support
N: Bill Pitts
E: wlp@mindspring.com
D: BedBug embedded debugger code
......
......@@ -340,6 +340,9 @@ Kshitij Gupta <kshitij@ti.com>
omap1510inn ARM925T
omap1610inn ARM926EJS
Dave Peverley <dpeverley@mpc-data.co.uk>
omap730p2 ARM926EJS
Nishant Kamat <nskamat@ti.com>
omap1610h2 ARM926EJS
......
......@@ -139,8 +139,8 @@ LIST_ARM7="B2 ep7312 impa7"
LIST_ARM9=" \
at91rm9200dk integratorcp integratorap \
omap1510inn omap1610h2 omap1610inn \
smdk2400 smdk2410 trab \
VCMA9 versatile \
omap730p2 smdk2400 smdk2410 \
trab VCMA9 versatile \
"
#########################################################################
......
......@@ -981,6 +981,8 @@ xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,
xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
SX1_config : unconfig
@./mkconfig $(@:_config=) arm arm925t sx1
......@@ -1011,6 +1013,18 @@ omap1610h2_cs3boot_config : unconfig
fi;
@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
omap730p2_config \
omap730p2_cs0boot_config \
omap730p2_cs3boot_config : unconfig
@if [ "$(findstring _cs0boot_, $@)" ] ; then \
echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
echo "... configured for CS0 boot"; \
else \
echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
echo "... configured for CS3 boot"; \
fi;
@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
smdk2400_config : unconfig
@./mkconfig $(@:_config=) arm arm920t smdk2400
......
......@@ -294,8 +294,9 @@ The following options need to be configured:
CONFIG_AT91RM9200DK, CONFIG_DNP1110, CONFIG_EP7312,
CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, CONFIG_IMPA7,
CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_LART,
CONFIG_LUBBOCK, CONFIG_SHANNON, CONFIG_SMDK2400,
CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9,
CONFIG_LUBBOCK, CONFIG_SHANNON, CONFIG_P2_OMAP730,
CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB,
CONFIG_VCMA9
MicroBlaze based boards:
------------------------
......@@ -2074,6 +2075,7 @@ configurations; the following names are supported:
FADS823_config NETVIA_config TQM860L_config
FADS850SAR_config omap1510inn_config WALNUT405_config
FADS860T_config omap1610h2_config ZPC1900_config
omap730p2_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for
......
......@@ -94,7 +94,7 @@ unsigned long flash_init (void)
/* Remap FLASH according to real size */
memctl->memc_or0 =
((((unsigned long) ~1) << i) & OR_AM_MSK) |
((((unsigned long) ~0) << i) & OR_AM_MSK) |
CFG_OR_TIMING_FLASH;
memctl->memc_br0 = CFG_BR0_PRELIM;
......
......@@ -349,10 +349,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
info->protect[i] = addr2[2] & 1;
}
/* issue bank reset to return to read mode */
addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0;
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
/* ? ? ? */
}
return (info->size);
......
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := omap730p2.o flash.o
SOBJS := platform.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
#
# (C) Copyright 2003
# Texas Instruments, <www.ti.com>
# Kshitij Gupta <Kshitij@ti.com>
#
# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
# Innovator has 1 bank of 256 MB SDRAM
# Physical Address:
# 1000'0000 to 2000'0000
#
#
# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
# (mem base + reserved)
#
# we load ourself to 1108'0000
#
#
TEXT_BASE = 0x11080000
This diff is collapsed.
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
*
* (C) Copyright 2003
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_OMAP730)
#include <./configs/omap730.h>
#endif
int test_boot_mode(void);
void spin_up_leds(void);
void flash__init (void);
void ether__init (void);
void set_muxconf_regs (void);
void peripheral_power_enable (void);
#define FLASH_ON_CS0 1
#define FLASH_ON_CS3 0
static inline void delay (unsigned long loops)
{
__asm__ volatile ("1:\n"
"subs %0, %1, #1\n"
"bne 1b":"=r" (loops):"0" (loops));
}
int test_boot_mode(void)
{
/* Check for CS0 and CS3 address decode swapping */
if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
return(FLASH_ON_CS3);
else
return(FLASH_ON_CS0);
}
/* Toggle backup LED indication */
void toggle_backup_led(void)
{
static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */
volatile unsigned int *IOConfReg;
IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
if (backupLEDState != 0) {
*IOConfReg &= (0xFFFFEFFF);
backupLEDState = 0;
} else {
*IOConfReg |= (0x00001000);
backupLEDState = 1;
}
}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init (void)
{
volatile unsigned int *IOConfReg;
DECLARE_GLOBAL_DATA_PTR;
/* arch number of OMAP 730 P2 Board - Same as the Innovator! */
gd->bd->bi_arch_number = 491;
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x10000100;
/* Configure MUX settings */
set_muxconf_regs ();
peripheral_power_enable ();
/* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
toggle_backup_led();
/* Hold GSM in reset until needed */
*((volatile unsigned short *)M_CTL) &= ~1;
/*
* CSx timings, GPIO Mux ... setup
*/
/* Flash: CS0 timings setup */
*((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
/* Ethernet support trough the debug board */
/* CS1 timings setup */
*((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
/* this speeds up your boot a quite a bit. However to make it
* work, you need make sure your kernel startup flush bug is fixed.
* ... rkw ...
*/
icache_enable ();
flash__init ();
ether__init ();
return 0;
}
int misc_init_r (void)
{
/* currently empty */
return (0);
}
/******************************
Routine:
Description:
******************************/
void flash__init (void)
{
unsigned int regval;
regval = *((volatile unsigned int *) EMIFS_CONFIG);
/* Turn off write protection for flash devices. */
regval = regval | 0x0001;
*((volatile unsigned int *) EMIFS_CONFIG) = regval;
}
/*************************************************************
Routine:ether__init
Description: take the Ethernet controller out of reset and wait
for the EEPROM load to complete.
*************************************************************/
void ether__init (void)
{
#define LAN_RESET_REGISTER 0x0400001c
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
do {
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
udelay (100);
} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
do {
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
udelay (100);
} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
#define ETH_CONTROL_REG 0x0400030b
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
udelay (100);
}
/******************************
Routine:
Description:
******************************/
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return 0;
}
/******************************************************
Routine: set_muxconf_regs
Description: Setting up the configuration Mux registers
specific to the hardware
*******************************************************/
void set_muxconf_regs (void)
{
volatile unsigned int *MuxConfReg;
/* set each registers to its reset value; */
/*
* Backup LED Indication
*/
/* Configure MUXed pin. Mode 6: GPIO_140 */
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
*MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */
*MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */
/* Configure GPIO_140 as output */
MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
*MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */
/*
* Configure GPIOs for battery charge & feedback
*/
/* Configure MUXed pin. Mode 6: GPIO_35 */
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
*MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */
*MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */
/* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
*MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */
*MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */
MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
*MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */
*MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */
/*
* Allow battery charge
*/
MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
*MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */
/*
* Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
* It is used as the Ethernet controller interrupt
*/
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
*MuxConfReg &= 0x1FFFFFFF;
}
/******************************************************
Routine: peripheral_power_enable
Description: Enable the power for UART1
*******************************************************/
void peripheral_power_enable (void)
{
volatile unsigned int *MuxConfReg;
/* Set up pins used by UART */
/* Start UART clock (48MHz) */
MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
*MuxConfReg &= (0xFFFFFFF7);
*MuxConfReg |= (0x00000008);
/* Get the UART pin in mode0 */
MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
*MuxConfReg &= (0xFF1FFFFF);
*MuxConfReg &= (0xF1FFFFFF);
}
/*
* Board specific setup info
*
* (C) Copyright 2003-2004
*
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
*
* Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
* (http://www.mpc-data.co.uk)
*
* TODO : Tidy up and change to use system register defines
* from omap730.h where possible.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#if defined(CONFIG_OMAP730)
#include <./configs/omap730.h>
#endif
_TEXT_BASE:
.word TEXT_BASE /* sdram load addr from config.mk */
.globl platformsetup
platformsetup:
/* Save callers address in r11 - r11 must never be modified */
mov r11, lr
/*------------------------------------------------------*
*mask all IRQs by setting all bits in the INTMR default*
*------------------------------------------------------*/
mov r1, #0xffffffff
ldr r0, =REG_IHL1_MIR
str r1, [r0]
ldr r0, =REG_IHL2_MIR
str r1, [r0]
/*------------------------------------------------------*
* Set up ARM CLM registers (IDLECT1) *
*------------------------------------------------------*/
ldr r0, REG_ARM_IDLECT1
ldr r1, VAL_ARM_IDLECT1
str r1, [r0]
/*------------------------------------------------------*
* Set up ARM CLM registers (IDLECT2) *
*------------------------------------------------------*/
ldr r0, REG_ARM_IDLECT2
ldr r1, VAL_ARM_IDLECT2
str r1, [r0]
/*------------------------------------------------------*
* Set up ARM CLM registers (IDLECT3) *
*------------------------------------------------------*/
ldr r0, REG_ARM_IDLECT3
ldr r1, VAL_ARM_IDLECT3
str r1, [r0]
mov r1, #0x01 /* PER_EN bit */
ldr r0, REG_ARM_RSTCT2
strh r1, [r0] /* CLKM; Peripheral reset. */
/* Set CLKM to Sync-Scalable */
/* I supposedly need to enable the dsp clock before switching */
mov r1, #0x1000
ldr r0, REG_ARM_SYSST
strh r1, [r0]
mov r0, #0x400
1:
subs r0, r0, #0x1 /* wait for any bubbles to finish */
bne 1b
ldr r1, VAL_ARM_CKCTL
ldr r0, REG_ARM_CKCTL
strh r1, [r0]
/* a few nops to let settle */
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
/* setup DPLL 1 */
/* Ramp up the clock to 96Mhz */
ldr r1, VAL_DPLL1_CTL
ldr r0, REG_DPLL1_CTL
strh r1, [r0]
ands r1, r1, #0x10 /* Check if PLL is enabled. */
beq lock_end /* Do not look for lock if BYPASS selected */
2:
ldrh r1, [r0]
ands r1, r1, #0x01 /* Check the LOCK bit.*/
beq 2b /* loop until bit goes hi. */
lock_end:
/*------------------------------------------------------*
* Turn off the watchdog during init... *
*------------------------------------------------------*/
ldr r0, REG_WATCHDOG
ldr r1, WATCHDOG_VAL1
str r1, [r0]
ldr r1, WATCHDOG_VAL2
str r1, [r0]
ldr r0, REG_WSPRDOG
ldr r1, WSPRDOG_VAL1
str r1, [r0]
ldr r0, REG_WWPSDOG
watch1Wait:
ldr r1, [r0]
tst r1, #0x10
bne watch1Wait
ldr r0, REG_WSPRDOG
ldr r1, WSPRDOG_VAL2
str r1, [r0]
ldr r0, REG_WWPSDOG
watch2Wait:
ldr r1, [r0]
tst r1, #0x10
bne watch2Wait
/* Set memory timings corresponding to the new clock speed */
/* Check execution location to determine current execution location
* and branch to appropriate initialization code.
*/
/* Compare physical SDRAM base & current execution location. */
and r0, pc, #0xF0000000
/* Compare. */
cmp r0, #0
/* Skip over EMIF-fast initialization if running from SDRAM. */
bne skip_sdram
/*
* Delay for SDRAM initialization.
*/
mov r3, #0x1800 /* value should be checked */
3:
subs r3, r3, #0x1 /* Decrement count */
bne 3b
ldr r0, REG_SDRAM_CONFIG
ldr r1, SDRAM_CONFIG_VAL
str r1, [r0]
ldr r0, REG_SDRAM_MRS_LEGACY
ldr r1, SDRAM_MRS_VAL
str r1, [r0]
skip_sdram:
common_tc:
/* slow interface */
ldr r1, VAL_TC_EMIFS_CS0_CONFIG
ldr r0, REG_TC_EMIFS_CS0_CONFIG
str r1, [r0] /* Chip Select 0 */
ldr r1, VAL_TC_EMIFS_CS1_CONFIG
ldr r0, REG_TC_EMIFS_CS1_CONFIG
str r1, [r0] /* Chip Select 1 */
ldr r1, VAL_TC_EMIFS_CS2_CONFIG
ldr r0, REG_TC_EMIFS_CS2_CONFIG
str r1, [r0] /* Chip Select 2 */
ldr r1, VAL_TC_EMIFS_CS3_CONFIG
ldr r0, REG_TC_EMIFS_CS3_CONFIG
str r1, [r0] /* Chip Select 3 */
/* 48MHz clock request for UART1 */
ldr r1, PERSEUS2_CONFIG_BASE
ldrh r0, [r1, #CONFIG_PCC_CONF]
orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R
strh r0, [r1, #CONFIG_PCC_CONF]
/* Initialize public and private rheas
* - set access factor 2 on both rhea / strobe
* - disable write buffer on strb0, enable write buffer on strb1
*/
ldr R0, REG_RHEA_PUB_CTL
ldr R1, REG_RHEA_PRIV_CTL
ldr R2, VAL_RHEA_CTL
strh R2, [R0]
strh R2, [R1]
mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */
strh R3, [R0, #0x08] /* arm rhea control reg */
strh R3, [R1, #0x08]
/* enable IRQ and FIQ */
mrs r4, CPSR
bic r4, r4, #IRQ_MASK
bic r4, r4, #FIQ_MASK
msr CPSR, r4
/* set TAP CONF to TRI EMULATION */
ldr r1, [r0, #CONFIG_MODE2]
bic r1, r1, #0x18
orr r1, r1, #0x10
str r1, [r0, #CONFIG_MODE2]
/* set tdbgen to 1 */
ldr r0, PERSEUS2_CONFIG_BASE
ldr r1, [r0, #CONFIG_MODE1]
mov r2, #0x10000
orr r1, r1, r2
str r1, [r0, #CONFIG_MODE1]
#ifdef CONFIG_P2_OMAP1610
/* inserting additional 2 clock cycle hold time for LAN */
ldr r0, REG_TC_EMIFS_CS1_ADVANCED
ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
str r1, [r0]
#endif
/* Start MPU Timer 1 */
ldr r0, REG_MPU_LOAD_TIMER
ldr r1, VAL_MPU_LOAD_TIMER