Commit a713ba92 authored by Poonam Aggrwal's avatar Poonam Aggrwal Committed by Kumar Gala
Browse files

85xx: Added single core members of FSL P1xx/P2xx processors series



P1011 - Single core variant of P1020
P2010 - Single core variant of P2020
Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent bf488bc0
...@@ -49,8 +49,10 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o ...@@ -49,8 +49,10 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_MPC8569) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_P1011) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
......
...@@ -64,10 +64,14 @@ struct cpu_type cpu_type_list [] = { ...@@ -64,10 +64,14 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8569, 8569_E, 1), CPU_TYPE_ENTRY(8569, 8569_E, 1),
CPU_TYPE_ENTRY(8572, 8572, 2), CPU_TYPE_ENTRY(8572, 8572, 2),
CPU_TYPE_ENTRY(8572, 8572_E, 2), CPU_TYPE_ENTRY(8572, 8572_E, 2),
CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P1011, P1011, 1),
CPU_TYPE_ENTRY(P2020, P2020_E, 2), CPU_TYPE_ENTRY(P1011, P1011_E, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2), CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2), CPU_TYPE_ENTRY(P1020, P1020_E, 2),
CPU_TYPE_ENTRY(P2010, P2010, 1),
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
#elif defined(CONFIG_MPC86xx) #elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2), CPU_TYPE_ENTRY(8641, 8641, 2),
......
...@@ -39,7 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; ...@@ -39,7 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
#define FSL_HW_NUM_LAWS 10 #define FSL_HW_NUM_LAWS 10
#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
defined(CONFIG_P2020) || defined(CONFIG_P1020) defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12 #define FSL_HW_NUM_LAWS 12
#else #else
#error FSL_HW_NUM_LAWS not defined for this platform #error FSL_HW_NUM_LAWS not defined for this platform
......
...@@ -1009,10 +1009,14 @@ ...@@ -1009,10 +1009,14 @@
#define SVR_8569_E 0x808800 #define SVR_8569_E 0x808800
#define SVR_8572 0x80E000 #define SVR_8572 0x80E000
#define SVR_8572_E 0x80E800 #define SVR_8572_E 0x80E800
#define SVR_P2020 0x80E200 #define SVR_P1011 0x80E500
#define SVR_P2020_E 0x80EA00 #define SVR_P1011_E 0x80ED00
#define SVR_P1020 0x80E400 #define SVR_P1020 0x80E400
#define SVR_P1020_E 0x80EC00 #define SVR_P1020_E 0x80EC00
#define SVR_P2010 0x80E300
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
#define SVR_8610 0x80A000 #define SVR_8610 0x80A000
#define SVR_8641 0x809000 #define SVR_8641 0x809000
......
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