Commit a76df709 authored by Gabriel Huau's avatar Gabriel Huau Committed by Stefano Babic
Browse files

mx6: add support of multi-processor command



This allows u-boot to load different OS or Bare Metal application on
different cores of the i.MX6 SoC.
For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.
Signed-off-by: default avatarGabriel Huau <contact@huau-gabriel.fr>
Acked-by: default avatarStefano Babic <sbabic@denx.de>
parent 015e215b
......@@ -10,3 +10,4 @@
obj-y := soc.o clock.o
obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
obj-$(CONFIG_MP) += mp.o
/*
* (C) Copyright 2014
* Gabriel Huau <contact@huau-gabriel.fr>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/imx-regs.h>
#define MAX_CPUS 4
static struct src *src = (struct src *)SRC_BASE_ADDR;
static uint32_t cpu_reset_mask[MAX_CPUS] = {
0, /* We don't really want to modify the cpu0 */
SRC_SCR_CORE_1_RESET_MASK,
SRC_SCR_CORE_2_RESET_MASK,
SRC_SCR_CORE_3_RESET_MASK
};
static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
0, /* We don't really want to modify the cpu0 */
SRC_SCR_CORE_1_ENABLE_MASK,
SRC_SCR_CORE_2_ENABLE_MASK,
SRC_SCR_CORE_3_ENABLE_MASK
};
int cpu_reset(int nr)
{
/* Software reset of the CPU N */
src->scr |= cpu_reset_mask[nr];
return 0;
}
int cpu_status(int nr)
{
printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
return 0;
}
int cpu_release(int nr, int argc, char *const argv[])
{
uint32_t boot_addr;
boot_addr = simple_strtoul(argv[0], NULL, 16);
switch (nr) {
case 1:
src->gpr3 = boot_addr;
break;
case 2:
src->gpr5 = boot_addr;
break;
case 3:
src->gpr7 = boot_addr;
break;
default:
return 1;
}
/* CPU N is ready to start */
src->scr |= cpu_ctrl_mask[nr];
return 0;
}
int is_core_valid(unsigned int core)
{
uint32_t nr_cores = get_nr_cpus();
if (core > nr_cores)
return 0;
return 1;
}
int cpu_disable(int nr)
{
/* Disable the CPU N */
src->scr &= ~cpu_ctrl_mask[nr];
return 0;
}
......@@ -35,6 +35,12 @@ struct scu_regs {
u32 fpga_rev;
};
u32 get_nr_cpus(void)
{
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
return readl(&scu->config) & 3;
}
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
......
......@@ -324,6 +324,19 @@
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_1_RESET_OFFSET 14
#define SRC_SCR_CORE_1_RESET_MASK (1<<SRC_SCR_CORE_1_RESET_OFFSET)
#define SRC_SCR_CORE_2_RESET_OFFSET 15
#define SRC_SCR_CORE_2_RESET_MASK (1<<SRC_SCR_CORE_2_RESET_OFFSET)
#define SRC_SCR_CORE_3_RESET_OFFSET 16
#define SRC_SCR_CORE_3_RESET_MASK (1<<SRC_SCR_CORE_3_RESET_OFFSET)
#define SRC_SCR_CORE_1_ENABLE_OFFSET 22
#define SRC_SCR_CORE_1_ENABLE_MASK (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
#define SRC_SCR_CORE_2_ENABLE_OFFSET 23
#define SRC_SCR_CORE_2_ENABLE_MASK (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
/* System Reset Controller (SRC) */
struct src {
u32 scr;
......
......@@ -14,6 +14,7 @@
#define soc_rev() (get_cpu_rev() & 0xFF)
#define is_soc_rev(rev) (soc_rev() - rev)
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
/* returns MXC_CPU_ value */
......
......@@ -34,6 +34,9 @@
#ifdef CONFIG_MPC5xxx
#include <mpc5xxx.h>
#endif
#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
#include <asm/mp.h>
#endif
#include <os.h>
#include <post.h>
......@@ -43,9 +46,6 @@
#include <watchdog.h>
#include <asm/errno.h>
#include <asm/io.h>
#ifdef CONFIG_MP
#include <asm/mp.h>
#endif
#include <asm/sections.h>
#ifdef CONFIG_X86
#include <asm/init_helpers.h>
......@@ -381,7 +381,7 @@ static int setup_dest_addr(void)
gd->ram_top = board_get_usable_ram_top(gd->mon_len);
gd->relocaddr = gd->ram_top;
debug("Ram top: %08lX\n", (ulong)gd->ram_top);
#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
#if (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
/*
* We need to make sure the location we intend to put secondary core
* boot code is reserved and not used by any part of u-boot
......
......@@ -28,4 +28,6 @@
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
#endif
#define CONFIG_MP
#endif
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