Commit a78ded13 authored by Wolfgang Denk's avatar Wolfgang Denk

Merge branch 'master' of git://git.denx.de/u-boot-ti

parents f8736c21 6696ac19
......@@ -26,7 +26,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libomap-common.a
SOBJS := reset.o
COBJS := timer.o
COBJS += syslib.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
......
......@@ -27,10 +27,12 @@
reset_cpu:
ldr r1, rstctl @ get addr for global reset
@ reg
mov r3, #0x2 @ full reset pll + mpu
ldr r3, rstbit @ sw reset bit
str r3, [r1] @ force reset
mov r0, r0
_loop_forever:
b _loop_forever
rstctl:
.word PRM_RSTCTRL
rstbit:
.word PRM_RSTCTRL_RESET
......@@ -23,8 +23,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>
#include <asm/arch/sys_proto.h>
/************************************************************
......
......@@ -32,7 +32,6 @@ COBJS += board.o
COBJS += clock.o
COBJS += gpio.o
COBJS += mem.o
COBJS += syslib.o
COBJS += sys_info.o
COBJS-$(CONFIG_EMIF4) += emif4.o
......
......@@ -119,41 +119,6 @@ void secureworld_exit()
__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}
/******************************************************************************
* Routine: setup_auxcr()
* Description: Write to AuxCR desired value using SMI.
* general use.
*****************************************************************************/
void setup_auxcr()
{
unsigned long i;
volatile unsigned int j;
/* Save r0, r12 and restore them after usage */
__asm__ __volatile__("mov %0, r12":"=r"(j));
__asm__ __volatile__("mov %0, r0":"=r"(i));
/*
* GP Device ROM code API usage here
* r12 = AUXCR Write function and r0 value
*/
__asm__ __volatile__("mov r12, #0x3");
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
/* Enabling ASA */
__asm__ __volatile__("orr r0, r0, #0x10");
/* Enable L1NEON */
__asm__ __volatile__("orr r0, r0, #1 << 5");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
/* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */
__asm__ __volatile__("mov r12, #0x2");
__asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2");
__asm__ __volatile__("orr r0, r0, #1 << 27");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
__asm__ __volatile__("mov r0, %0":"=r"(i));
__asm__ __volatile__("mov r12, %0":"=r"(j));
}
/******************************************************************************
* Routine: try_unlock_sram()
* Description: If chip is GP/EMU(special) type, unlock the SRAM for
......
......@@ -43,6 +43,7 @@
.global invalidate_dcache
.global l2_cache_enable
.global l2_cache_disable
.global setup_auxcr
/*
* invalidate_dcache()
......@@ -128,64 +129,56 @@ finished_inval:
ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
l2_cache_enable:
stmfd r13!, {r0, r1, r2, lr}
@ ES2 onwards we can disable/enable L2 ourselves
l2_cache_set:
stmfd r13!, {r4 - r6, lr}
mov r5, r0
bl get_cpu_rev
cmp r0, #CPU_3XX_ES20
blt l2_cache_disable_EARLIER_THAN_ES2
mrc 15, 0, r3, cr1, cr0, 1
orr r3, r3, #2
mcr 15, 0, r3, cr1, cr0, 1
b l2_cache_enable_END
l2_cache_enable_EARLIER_THAN_ES2:
@ Save r0, r12 and restore them after usage
mov r3, ip
str r3, [sp, #4]
mov r3, r0
@
mov r4, r0
bl get_cpu_family
@ ES2 onwards we can disable/enable L2 ourselves
cmp r0, #CPU_OMAP34XX
cmpeq r4, #CPU_3XX_ES10
mrc 15, 0, r0, cr1, cr0, 1
bic r0, r0, #2
orr r0, r0, r5, lsl #1
mcreq 15, 0, r0, cr1, cr0, 1
@ GP Device ROM code API usage here
@ r12 = AUXCR Write function and r0 value
@
mov ip, #3
mrc 15, 0, r0, cr1, cr0, 1
orr r0, r0, #2
@ SMI instruction to call ROM Code API
.word 0xe1600070
mov r0, r3
mov ip, r3
str r3, [sp, #4]
l2_cache_enable_END:
ldmfd r13!, {r1, r2, r3, pc}
@ SMCNE instruction to call ROM Code API
.word 0x11600070
ldmfd r13!, {r4 - r6, pc}
l2_cache_enable:
mov r0, #1
b l2_cache_set
l2_cache_disable:
stmfd r13!, {r0, r1, r2, lr}
@ ES2 onwards we can disable/enable L2 ourselves
bl get_cpu_rev
cmp r0, #CPU_3XX_ES20
blt l2_cache_disable_EARLIER_THAN_ES2
mrc 15, 0, r3, cr1, cr0, 1
bic r3, r3, #2
mcr 15, 0, r3, cr1, cr0, 1
b l2_cache_disable_END
l2_cache_disable_EARLIER_THAN_ES2:
@ Save r0, r12 and restore them after usage
mov r3, ip
str r3, [sp, #4]
mov r3, r0
@
@ GP Device ROM code API usage here
@ r12 = AUXCR Write function and r0 value
@
mov ip, #3
mrc 15, 0, r0, cr1, cr0, 1
bic r0, r0, #2
@ SMI instruction to call ROM Code API
.word 0xe1600070
mov r0, r3
mov ip, r3
str r3, [sp, #4]
l2_cache_disable_END:
ldmfd r13!, {r1, r2, r3, pc}
mov r0, #0
b l2_cache_set
/******************************************************************************
* Routine: setup_auxcr()
* Description: Write to AuxCR desired value using SMI.
* general use.
*****************************************************************************/
setup_auxcr:
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
and r2, r0, #0x00f00000 @ variant
and r3, r0, #0x0000000f @ revision
orr r1, r3, r2, lsr #20-4 @ combine variant and revision
mov r12, #0x3
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #0x10 @ Enable ASA
@ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
cmp r1, #0x21
orrlt r0, r0, #1 << 5
.word 0xE1600070 @ SMC
mov r12, #0x2
mrc p15, 1, r0, c9, c0, 2
@ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
cmp r1, #0x21
orrlt r0, r0, #1 << 27
.word 0xE1600070 @ SMC
bx lr
This diff is collapsed.
......@@ -359,3 +359,72 @@ per_dpll_param:
get_per_dpll_param:
adr r0, per_dpll_param
mov pc, lr
/*
* Tables for 36XX/37XX devices
*
*/
mpu_36x_dpll_param:
/* 12MHz */
.word 50, 0, 0, 1
/* 13MHz */
.word 600, 12, 0, 1
/* 19.2MHz */
.word 125, 3, 0, 1
/* 26MHz */
.word 300, 12, 0, 1
/* 38.4MHz */
.word 125, 7, 0, 1
iva_36x_dpll_param:
/* 12MHz */
.word 130, 2, 0, 1
/* 13MHz */
.word 20, 0, 0, 1
/* 19.2MHz */
.word 325, 11, 0, 1
/* 26MHz */
.word 10, 0, 0, 1
/* 38.4MHz */
.word 325, 23, 0, 1
core_36x_dpll_param:
/* 12MHz */
.word 100, 2, 0, 1
/* 13MHz */
.word 400, 12, 0, 1
/* 19.2MHz */
.word 375, 17, 0, 1
/* 26MHz */
.word 200, 12, 0, 1
/* 38.4MHz */
.word 375, 35, 0, 1
per_36x_dpll_param:
/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
.word 13000, 864, 12, 9, 16, 9, 4, 3, 1
.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
.globl get_36x_mpu_dpll_param
get_36x_mpu_dpll_param:
adr r0, mpu_36x_dpll_param
mov pc, lr
.globl get_36x_iva_dpll_param
get_36x_iva_dpll_param:
adr r0, iva_36x_dpll_param
mov pc, lr
.globl get_36x_core_dpll_param
get_36x_core_dpll_param:
adr r0, core_36x_dpll_param
mov pc, lr
.globl get_36x_per_dpll_param
get_36x_per_dpll_param:
adr r0, per_36x_dpll_param
mov pc, lr
......@@ -107,18 +107,12 @@ u32 get_sdr_cs_offset(u32 cs)
/*
* do_sdrc_init -
* - Initialize the SDRAM for use.
* - Sets up SDRC timings for CS0
* - code called once in C-Stack only context for CS0 and a possible 2nd
* time depending on memory configuration from stack+global context
*/
void do_sdrc_init(u32 cs, u32 early)
{
struct sdrc_actim *sdrc_actim_base;
if (cs)
sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
else
sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
if (early) {
/* reset sdrc controller */
......@@ -138,24 +132,29 @@ void do_sdrc_init(u32 cs, u32 early)
sdelay(0x20000);
}
writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
writel(CMD_NOP, &sdrc_base->cs[cs].manual);
writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
/*
* CAS latency 3, Write Burst = Read Burst, Serial Mode,
* Burst length = 4
* SDRC timings are set up by x-load or config header
* We don't need to redo them here.
* Older x-loads configure only CS0
* configure CS1 to handle this ommission
*/
writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
if (cs) {
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
writel(readl(&sdrc_base->cs[CS0].mcfg),
&sdrc_base->cs[CS1].mcfg);
writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
&sdrc_base->cs[CS1].rfr_ctrl);
writel(readl(&sdrc_actim_base0->ctrla),
&sdrc_actim_base1->ctrla);
writel(readl(&sdrc_actim_base0->ctrlb),
&sdrc_actim_base1->ctrlb);
}
/*
* Test ram in this bank
* Disable if bad or not present
*/
if (!mem_ok(cs))
writel(0, &sdrc_base->cs[cs].mcfg);
}
......
......@@ -38,7 +38,10 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
"2.0",
"2.1",
"3.0",
"3.1"};
"3.1",
"UNKNOWN",
"UNKNOWN",
"3.1.2"};
/*****************************************************************
* dieid_num_r(void) - read and set die ID
......@@ -75,32 +78,81 @@ u32 get_cpu_type(void)
}
/******************************************
* get_cpu_rev(void) - extract version info
* get_cpu_id(void) - extract cpu id
* returns 0 for ES1.0, cpuid otherwise
******************************************/
u32 get_cpu_rev(void)
u32 get_cpu_id(void)
{
u32 cpuid = 0;
struct ctrl_id *id_base;
u32 cpuid = 0;
/*
* On ES1.0 the IDCODE register is not exposed on L4
* so using CPU ID to differentiate between ES1.0 and > ES1.0.
*/
__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
if ((cpuid & 0xf) == 0x0)
return CPU_3XX_ES10;
else {
if ((cpuid & 0xf) == 0x0) {
return 0;
} else {
/* Decode the IDs on > ES1.0 */
id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
cpuid = readl(&id_base->idcode);
}
/* Some early ES2.0 seem to report ID 0, fix this */
if(cpuid == 0)
cpuid = CPU_3XX_ES20;
return cpuid;
}
return cpuid;
/******************************************
* get_cpu_family(void) - extract cpu info
******************************************/
u32 get_cpu_family(void)
{
u16 hawkeye;
u32 cpu_family;
u32 cpuid = get_cpu_id();
if (cpuid == 0)
return CPU_OMAP34XX;
hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
switch (hawkeye) {
case HAWKEYE_OMAP34XX:
cpu_family = CPU_OMAP34XX;
break;
case HAWKEYE_AM35XX:
cpu_family = CPU_AM35XX;
break;
case HAWKEYE_OMAP36XX:
cpu_family = CPU_OMAP36XX;
break;
default:
cpu_family = CPU_OMAP34XX;
}
return cpu_family;
}
/******************************************
* get_cpu_rev(void) - extract version info
******************************************/
u32 get_cpu_rev(void)
{
u32 cpuid = get_cpu_id();
if (cpuid == 0)
return CPU_3XX_ES10;
else
return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
}
/*****************************************************************
* get_sku_id(void) - read sku_id to get info on max clock rate
*****************************************************************/
u32 get_sku_id(void)
{
struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
return readl(&id_base->sku_id) & SKUID_CLK_MASK;
}
/***************************************************************************
......@@ -213,24 +265,66 @@ u32 get_device_type(void)
*/
int print_cpuinfo (void)
{
char *cpu_s, *sec_s;
char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
switch (get_cpu_family()) {
case CPU_OMAP34XX:
cpu_family_s = "OMAP";
switch (get_cpu_type()) {
case OMAP3503:
cpu_s = "3503";
break;
case OMAP3515:
cpu_s = "3515";
break;
case OMAP3525:
cpu_s = "3525";
break;
case OMAP3530:
cpu_s = "3530";
break;
default:
cpu_s = "35XX";
break;
}
if ((get_cpu_rev() >= CPU_3XX_ES31) &&
(get_sku_id() == SKUID_CLK_720MHZ))
max_clk = "720 mHz";
else
max_clk = "600 mHz";
switch (get_cpu_type()) {
case OMAP3503:
cpu_s = "3503";
break;
case OMAP3515:
cpu_s = "3515";
case CPU_AM35XX:
cpu_family_s = "AM";
switch (get_cpu_type()) {
case AM3505:
cpu_s = "3505";
break;
case AM3517:
cpu_s = "3517";
break;
default:
cpu_s = "35XX";
break;
}
max_clk = "600 Mhz";
break;
case OMAP3525:
cpu_s = "3525";
break;
case OMAP3530:
cpu_s = "3530";
case CPU_OMAP36XX:
cpu_family_s = "OMAP";
switch (get_cpu_type()) {
case OMAP3730:
cpu_s = "3630/3730";
break;
default:
cpu_s = "36XX/37XX";
break;
}
max_clk = "1 Ghz";
break;
default:
cpu_family_s = "OMAP";
cpu_s = "35XX";
break;
max_clk = "600 Mhz";
}
switch (get_device_type()) {
......@@ -250,8 +344,9 @@ int print_cpuinfo (void)
sec_s = "?";
}
printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
cpu_s, sec_s, rev_s[get_cpu_rev()]);
printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
cpu_family_s, cpu_s, sec_s,
rev_s[get_cpu_rev()], max_clk);
return 0;
}
......
......@@ -51,12 +51,29 @@ typedef struct {
unsigned int m2;
} dpll_param;
struct dpll_per_36x_param {
unsigned int sys_clk;
unsigned int m;
unsigned int n;
unsigned int m2;
unsigned int m3;
unsigned int m4;
unsigned int m5;
unsigned int m6;
unsigned int m2div;
};
/* Following functions are exported from lowlevel_init.S */
extern dpll_param *get_mpu_dpll_param(void);
extern dpll_param *get_iva_dpll_param(void);
extern dpll_param *get_core_dpll_param(void);
extern dpll_param *get_per_dpll_param(void);
extern dpll_param *get_36x_mpu_dpll_param(void);
extern dpll_param *get_36x_iva_dpll_param(void);
extern dpll_param *get_36x_core_dpll_param(void);
extern dpll_param *get_36x_per_dpll_param(void);
extern void *_end_vect, *_start;
#endif
......@@ -282,4 +282,31 @@
#define PER_FSEL_38P4 0x07
#define PER_M2_38P4 0x09
/* 36XX PER DPLL */
#define PER_36XX_M_12 0x1B0
#define PER_36XX_N_12 0x05
#define PER_36XX_FSEL_12 0x07
#define PER_36XX_M2_12 0x09
#define PER_36XX_M_13 0x360
#define PER_36XX_N_13 0x0C
#define PER_36XX_FSEL_13 0x03
#define PER_36XX_M2_13 0x09
#define PER_36XX_M_19P2 0x1C2
#define PER_36XX_N_19P2 0x09
#define PER_36XX_FSEL_19P2 0x07
#define PER_36XX_M2_19P2 0x09
#define PER_36XX_M_26 0x1B0
#define PER_36XX_N_26 0x0C
#define PER_36XX_FSEL_26 0x07
#define PER_36XX_M2_26 0x09
#define PER_36XX_M_38P4 0x1C2
#define PER_36XX_N_38P4 0x13
#define PER_36XX_FSEL_38P4 0x07
#define PER_36XX_M2_38P4 0x09
#endif /* endif _CLOCKS_OMAP3_H_ */
......@@ -60,19 +60,14 @@ struct ctrl {
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
/* cpu type */
#define OMAP3503 0x5c00
#define OMAP3515 0x1c00
#define OMAP3525 0x4c00
#define OMAP3530 0x0c00
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct ctrl_id {
u8 res1[0x4];
u32 idcode; /* 0x04 */
u32 prod_id; /* 0x08 */
u8 res2[0x0C];
u32 sku_id; /* 0x0c */
u8 res2[0x08];
u32 die_id_0; /* 0x18 */
u32 die_id_1; /* 0x1C */
u32 die_id_2; /* 0x20 */
......@@ -89,6 +84,11 @@ struct ctrl_id {
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
/* device speed */
#define SKUID_CLK_MASK 0xf
#define SKUID_CLK_600MHZ 0x0
#define SKUID_CLK_720MHZ 0x8
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0 0x60
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
......@@ -419,6 +419,7 @@ struct prm {
};
#else /* __ASSEMBLY__ */
#define PRM_RSTCTRL 0x48307250
#define PRM_RSTCTRL_RESET 0x04
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
......
......@@ -176,11 +176,41 @@ struct gpio {
#define CPU_3XX_ES21 2
#define CPU_3XX_ES30 3
#define CPU_3XX_ES31 4
#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1)
#define CPU_3XX_ES312 7
#define CPU_3XX_MAX_REV 8
#define CPU_3XX_ID_SHIFT 28
#define WIDTH_8BIT 0x0000
#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
/*
* Hawkeye values
*/
#define HAWKEYE_OMAP34XX 0xb7ae
#define HAWKEYE_AM35XX 0xb868
#define HAWKEYE_OMAP36XX 0xb891
#define HAWKEYE_SHIFT 12
/*
* Define CPU families
*/
#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
#define CPU_AM35XX 0x3500 /* AM35xx devices */
#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
/*
* Control status register values corresponding to cpu variants
*/
#define OMAP3503 0x5c00
#define OMAP3515 0x1c00
#define OMAP3525 0x4c00
#define OMAP3530 0x0c00
#define AM3505 0x5c00
#define AM3517 0x1c00
#define OMAP3730 0x0c00
#endif
......@@ -41,7 +41,9 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
void watchdog_init(void);
void set_muxconf_regs(void);
u32 get_cpu_family(void);
u32 get_cpu_rev(void);
u32 get_sku_id(void);
u32 get_mem_type(void);