Commit a880cf3e authored by Kumar Gala's avatar Kumar Gala
Browse files

ppc/p4080: CoreNet platfrom style CCSRBAR setting



On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 418ec858
......@@ -24,6 +24,51 @@
DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
#ifdef CONFIG_FSL_CORENET
static void setup_ccsrbar(void)
{
u32 temp;
volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
volatile ccsr_local_t *ccm;
/*
* We can't call set_law() because we haven't moved
* CCSR yet.
*/
ccm = (void *)ccsr_virt;
out_be32(&ccm->law[0].lawbarh,
(u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
out_be32(&ccm->law[0].lawar,
LAW_EN | (0x1e << 20) | LAW_SIZE_4K);
in_be32((u32 *)(ccsr_virt + 0));
in_be32((u32 *)(ccsr_virt + 1));
isync();
ccm = (void *)CONFIG_SYS_CCSRBAR;
/* Now use the temporary LAW to move CCSR */
out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
out_be32(&ccm->ccsrar, CCSRAR_C);
temp = in_be32(&ccm->ccsrar);
disable_law(0);
}
#else
static void setup_ccsrbar(void)
{
u32 temp;
volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
temp = in_be32(ccsr_virt);
out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
}
#endif
#endif
/* We run cpu_init_early_f in AS = 1 */
void cpu_init_early_f(void)
{
......@@ -50,24 +95,15 @@ void cpu_init_early_f(void)
/* set up CCSR if we want it moved */
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
{
u32 temp;
volatile u32 *ccsr_virt =
(volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
/* mas1 is the same as above */
mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G);
mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0,
MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
write_tlb(mas0, mas1, mas2, mas3, mas7);
temp = in_be32(ccsr_virt);
out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
}
mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
/* mas1 is the same as above */
mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G);
mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
write_tlb(mas0, mas1, mas2, mas3, mas7);
setup_ccsrbar();
#endif
init_laws();
......
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