Commit a8fc12eb authored by Anton Staaf's avatar Anton Staaf Committed by Wolfgang Denk
Browse files

m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment


Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jason Jin <jason.jin@freescale.com>
parent 44d6cbb6
......@@ -207,4 +207,14 @@ void dcache_invalid(void);
#endif
/*
* m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer
* alignment unless the board configuration has specified a new value.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 16
#endif
#endif /* __CACHE_H */
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