Commit aa245090 authored by wdenk's avatar wdenk
Browse files

Patch by Tolunay Orkun, 14 May 2004:

Add support for Cogent CSB472 board (8MB Flash Rev)
parent aa5590b6
......@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Tolunay Orkun, 14 May 2004:
Add support for Cogent CSB472 board (8MB Flash Rev)
* Patch by Thomas Viehweger, 14 May 2004:
- flash.h: more flash types added
- immap_8260.h: some bits added (useful for RMII)
......
......@@ -269,7 +269,7 @@ W: www.elinos.com
N: Tolunay Orkun
E: torkun@nextio.com
D: Support for Cogent CSB272 board
D: Support for Cogent CSB272 & CSB472 boards
N: Keith Outwater
E: keith_outwater@mvis.com
......
......@@ -193,7 +193,8 @@ Scott McNutt <smcnutt@artesyncp.com>
EBONY PPC440GP
Tolunay Orkun <torkun@nextio.com>
csb272 PPC4xx
csb272 PPC405GP
csb472 PPC405GP
Keith Outwater <Keith_Outwater@mvis.com>
......
......@@ -60,13 +60,13 @@ LIST_4xx=" \
ADCIOP AR405 ASH405 BUBINGA405EP \
CANBT CPCI405 CPCI4052 CPCI405AB \
CPCI440 CPCIISER4 CRAYL1 csb272 \
DASA_SIM DP405 DU405 EBONY \
ERIC EXBITGEN HUB405 JSE \
MIP405 MIP405T ML2 ml300 \
OCOTEA OCRTC ORSG PCI405 \
PIP405 PLU405 PMC405 PPChameleonEVB \
VOH405 W7OLMC W7OLMG WALNUT405 \
XPEDITE1K \
csb472 DASA_SIM DP405 DU405 \
EBONY ERIC EXBITGEN HUB405 \
JSE MIP405 MIP405T ML2 \
ml300 OCOTEA OCRTC ORSG \
PCI405 PIP405 PLU405 PMC405 \
PPChameleonEVB VOH405 W7OLMC W7OLMG \
WALNUT405 XPEDITE1K \
"
#########################################################################
......
......@@ -602,6 +602,9 @@ CRAYL1_config: unconfig
csb272_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx csb272
csb472_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx csb472
DASA_SIM_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd
......
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
#OBJS = $(BOARD).o flash.o
#OBJS = $(BOARD).o strataflash.o
OBJS = $(BOARD).o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2004
# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Cogent CSB472 board
#
LDFLAGS += $(LINKER_UNDEFS)
TEXT_BASE := 0xFFFC0000
#TEXT_BASE := 0x00100000
PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
/*
* (C) Copyright 2004
* Tolunay Orkun, Nextio Inc., torkun@nextio.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <i2c.h>
#include <miiphy.h>
#include <405gp_enet.h>
/*
* board_early_init_f: do early board initialization
*
*/
int board_early_init_f(void)
{
/*-------------------------------------------------------------------------+
| Interrupt controller setup for the Walnut board.
| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
| IRQ 16 405GP internally generated; active low; level sensitive
| IRQ 17-24 RESERVED
| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
| IRQ 27 (EXT IRQ 2) Not Used
| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
| Note for Walnut board:
| An interrupt taken for the FPGA (IRQ 25) indicates that either
| the Mouse, Keyboard, IRDA, or External Expansion caused the
| interrupt. The FPGA must be read to determine which device
| caused the interrupt. The default setting of the FPGA clears
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtebc (epcr, 0xa8400000); /* EBC always driven */
return 0; /* success */
}
/*
* checkboard: identify/verify the board we are running
*
* Remark: we just assume it is correct board here!
*
*/
int checkboard(void)
{
printf("BOARD: Cogent CSB472\n");
return 0; /* success */
}
/*
* initram: Determine the size of mounted DRAM
*
* Size is determined by reading SDRAM configuration registers as
* configured by initialization code
*
*/
long initdram (int board_type)
{
ulong tot_size;
ulong bank_size;
ulong tmp;
tot_size = 0;
mtdcr (memcfga, mem_mb0cf);
tmp = mfdcr (memcfgd);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb1cf);
tmp = mfdcr (memcfgd);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb2cf);
tmp = mfdcr (memcfgd);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
mtdcr (memcfga, mem_mb3cf);
tmp = mfdcr (memcfgd);
if (tmp & 0x00000001) {
bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
tot_size += bank_size;
}
return tot_size;
}
/*
* last_stage_init: final configurations (such as PHY etc)
*
*/
int last_stage_init(void)
{
/* initialize the PHY */
miiphy_reset(CONFIG_PHY_ADDR);
miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
return 0; /* success */
}
/******************************************************************************
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
* copying it, modifying it, compiling it, and redistributing it either
* with or without modifications. No license under IBM patents or
* patent applications is to be implied by the copyright license.
*
* Any user of this software should understand that IBM cannot provide
* technical support for this software and will not be responsible for
* any consequences resulting from the use of this software.
*
* Any person who transfers this source code or any derivative work
* must include the IBM copyright notice, this paragraph, and the
* preceding two paragraphs in the transferred software.
*
* COPYRIGHT I B M CORPORATION 1995
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*
*****************************************************************************/
#include <config.h>
#include <ppc4xx.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#define LI32(reg,val) \
addis reg,0,val@h;\
ori reg,reg,val@l
#define WDCR_EBC(reg,val) \
addi r4,0,reg;\
mtdcr ebccfga,r4;\
addis r4,0,val@h;\
ori r4,r4,val@l;\
mtdcr ebccfgd,r4
#define WDCR_SDRAM(reg,val) \
addi r4,0,reg;\
mtdcr memcfga,r4;\
addis r4,0,val@h;\
ori r4,r4,val@l;\
mtdcr memcfgd,r4
/******************************************************************************
* Function: ext_bus_cntlr_init
*
* Description: Configures EBC Controller and a few basic chip selects.
*
* CS0 is setup to get the Boot Flash out of the addresss range
* so that we may setup a stack. CS7 is setup so that we can
* access and reset the hardware watchdog.
*
* IMPORTANT: For pass1 this code must run from
* cache since you can not reliably change a peripheral banks
* timing register (pbxap) while running code from that bank.
* For ex., since we are running from ROM on bank 0, we can NOT
* execute the code that modifies bank 0 timings from ROM, so
* we run it from cache.
*
* Notes: Does NOT use the stack.
*****************************************************************************/
.section ".text"
.align 2
.globl ext_bus_cntlr_init
.type ext_bus_cntlr_init, @function
ext_bus_cntlr_init:
mflr r0
/********************************************************************
* Prefetch entire ext_bus_cntrl_init function into the icache.
* This is necessary because we are going to change the same CS we
* are executing from. Otherwise a CPU lockup may occur.
*******************************************************************/
bl ..getAddr
..getAddr:
mflr r3 /* get address of ..getAddr */
/* Calculate number of cache lines for this function */
addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
mtctr r4
..ebcloop:
icbt r0, r3 /* prefetch cache line for addr in r3*/
addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
bdnz ..ebcloop /* continue for $CTR cache lines */
/********************************************************************
* Delay to ensure all accesses to ROM are complete before changing
* bank 0 timings. 200usec should be enough.
* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
*******************************************************************/
addis r3, 0, 0x0
ori r3, r3, 0xA000 /* wait 200us from reset */
mtctr r3
..spinlp:
bdnz ..spinlp /* spin loop */
/********************************************************************
* SETUP CPC0_CR0
*******************************************************************/
LI32(r4, 0x00c01030)
mtdcr cntrl0, r4
/********************************************************************
* Setup CPC0_CR1: Change PCIINT signal to PerWE
*******************************************************************/
mfdcr r4, cntrl1
ori r4, r4, 0x4000
mtdcr cntrl1, r4
/********************************************************************
* Setup External Bus Controller (EBC).
*******************************************************************/
WDCR_EBC(epcr, 0xd84c0000)
/********************************************************************
* Memory Bank 0 (Intel 28F640J3 Flash) initialization
*******************************************************************/
/*WDCR_EBC(pb0ap, 0x03055200)*/
/*WDCR_EBC(pb0ap, 0x04055200)*/
WDCR_EBC(pb0ap, 0x08055200)
WDCR_EBC(pb0cr, 0xff87a000)
/********************************************************************
* Memory Bank 3 (Xilinx XC95144 CPLD) initialization
*******************************************************************/
/*WDCR_EBC(pb3ap, 0x07869200)*/
WDCR_EBC(pb3ap, 0x04055200)
WDCR_EBC(pb3cr, 0xff01c000)
/********************************************************************
* Memory Bank 1,2,4-7 (Unused) initialization
*******************************************************************/
WDCR_EBC(pb1ap, 0)
WDCR_EBC(pb1cr, 0)
WDCR_EBC(pb2ap, 0)
WDCR_EBC(pb2cr, 0)
WDCR_EBC(pb4ap, 0)
WDCR_EBC(pb4cr, 0)
WDCR_EBC(pb5ap, 0)
WDCR_EBC(pb5cr, 0)
WDCR_EBC(pb6ap, 0)
WDCR_EBC(pb6cr, 0)
WDCR_EBC(pb7ap, 0)
WDCR_EBC(pb7cr, 0)
/* We are all done */
mtlr r0 /* Restore link register */
blr /* Return to calling function */
.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
/* end ext_bus_cntlr_init() */
/******************************************************************************
* Function: sdram_init
*
* Description: Configures SDRAM memory banks.
*
* Notes: Does NOT use the stack.
*****************************************************************************/
.section ".text"
.align 2
.globl sdram_init
.type sdram_init, @function
sdram_init:
/*
* Disable memory controller to allow
* values to be changed.
*/
WDCR_SDRAM(mem_mcopt1, 0x00000000)
/*
* Configure Memory Banks
*/
WDCR_SDRAM(mem_mb0cf, 0x00062001)
WDCR_SDRAM(mem_mb1cf, 0x00000000)
WDCR_SDRAM(mem_mb2cf, 0x00000000)
WDCR_SDRAM(mem_mb3cf, 0x00000000)
/*
* Set up SDTR1 (SDRAM Timing Register)
*/
WDCR_SDRAM(mem_sdtr1, 0x00854009)
/*
* Set RTR (Refresh Timing Register)
*/
WDCR_SDRAM(mem_rtr, 0x10000000)
/* WDCR_SDRAM(mem_rtr, 0x05f00000) */
/********************************************************************
* Delay to ensure 200usec have elapsed since reset. Assume worst
* case that the core is running 200Mhz:
* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
*******************************************************************/
addis r3, 0, 0x0000
ori r3, r3, 0xA000 /* Wait >200us from reset */
mtctr r3
..spinlp2:
bdnz ..spinlp2 /* spin loop */
/********************************************************************
* Set memory controller options reg, MCOPT1.
*******************************************************************/
WDCR_SDRAM(mem_mcopt1,0x80800000)
..sdri_done:
blr /* Return to calling function */
.Lfe1: .size sdram_init,.Lfe1-sdram_init
/* end sdram_init() */
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/csb472/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_ppc/board.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);