Commit ab77f241 authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-ti

parents d928664f fa58b102
......@@ -76,13 +76,13 @@ static void configure_mr(int nr, u32 cs)
}
/*
* Configure EMIF4D5 registers and MR registers
* Configure EMIF4D5 registers and MR registers For details about these magic
* values please see the EMIF registers section of the TRM.
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
......@@ -106,10 +106,45 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
}
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
/*
* Sequence to ensure that the PHY is in a known state prior to
* startting hardware leveling. Also acts as to latch some state from
* the EMIF into the PHY.
*/
writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
EMIF_REG_INITREF_DIS_MASK);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
/* Perform hardware leveling. */
udelay(1000);
writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
/* Enable read leveling */
writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
/*
* Enable full read and write leveling. Wait for read and write
* leveling bit to clear RDWRLVLFULL_START bit 31
*/
while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
;
/* Check the timeout register to see if leveling is complete */
if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
puts("DDR3 H/W leveling incomplete with errors\n");
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
configure_mr(nr, 0);
......@@ -123,21 +158,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
void config_sdram(const struct emif_regs *regs, int nr)
{
if (regs->zq_config) {
/*
* A value of 0x2800 for the REF CTRL will give us
* about 570us for a delay, which will be long enough
* to configure things.
*/
writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
}
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
}
/**
......@@ -153,46 +182,55 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}
void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
}
/*
* Configure EXT PHY registers
* Configure EXT PHY registers for hardware leveling
*/
static void ext_phy_settings(const struct emif_regs *regs, int nr)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
u32 size;
ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
emif_ext_phy_ctrl_base =
(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
/* Configure external phy control timing registers */
for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
}
/*
* external phy 6-24 registers do not change with
* ddr frequency
* Enable hardware leveling on the EMIF. For details about these
* magic values please see the EMIF registers section of the TRM.
*/
emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
if (!size)
return;
writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
for (i = 0; i < size; i++) {
writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
}
/*
* Sequence to ensure that the PHY is again in a known state after
* hardware leveling.
*/
writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
}
/**
......@@ -201,11 +239,17 @@ static void ext_phy_settings(const struct emif_regs *regs, int nr)
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
/*
* disable initialization and refreshes for now until we
* Disable initialization and refreshes for now until we
* finish programming EMIF regs.
* Also set time between rising edge of DDR_RESET to rising
* edge of DDR_CKE to > 500us per memory spec.
*/
#ifndef CONFIG_AM43XX
setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
EMIF_REG_INITREF_DIS_MASK);
#endif
if (regs->zq_config)
writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);
......
......@@ -112,17 +112,20 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
;
writel(0x80000000, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Allow EMIF to control DDR_RESET */
writel(0x00000000, &ddrctrl->ddrioctrl);
#endif
/* Program EMIF instance */
......
......@@ -219,6 +219,12 @@ struct cm_dpll {
unsigned int resv4[2];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
struct prm_device_inst {
unsigned int prm_rstctrl;
unsigned int prm_rsttime;
unsigned int prm_rstst;
};
#else
/* Encapsulating core pll registers */
struct cm_wkuppll {
......@@ -386,6 +392,11 @@ struct cm_device_inst {
unsigned int cm_dll_ctrl;
};
struct prm_device_inst {
unsigned int prm_rstctrl;
unsigned int prm_rstst;
};
struct cm_dpll {
unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x04 */
......
......@@ -39,6 +39,7 @@
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x44E10E0C
#define VTP1_CTRL_ADDR 0x48140E10
#define PRM_DEVICE_INST 0x44E00F00
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x44E12000
......
......@@ -71,6 +71,7 @@
#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
#define USBPHYOCPSCP_MODULE_EN (1 << 1)
#define CM_DEVICE_INST 0x44df4100
#define PRM_DEVICE_INST 0x44df4000
/* Control status register */
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
......
......@@ -650,8 +650,8 @@ struct emif_reg_struct {
u32 emif_rd_wr_exec_thresh;
u32 emif_cos_config;
u32 padding9[6];
u32 emif_ddr_phy_status[21];
u32 padding10[27];
u32 emif_ddr_phy_status[28];
u32 padding10[20];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
......@@ -700,9 +700,36 @@ struct emif_reg_struct {
u32 emif_ddr_ext_phy_ctrl_23_shdw;
u32 emif_ddr_ext_phy_ctrl_24;
u32 emif_ddr_ext_phy_ctrl_24_shdw;
u32 padding[22];
u32 emif_ddr_fifo_misaligned_clear_1;
u32 emif_ddr_fifo_misaligned_clear_2;
u32 emif_ddr_ext_phy_ctrl_25;
u32 emif_ddr_ext_phy_ctrl_25_shdw;
u32 emif_ddr_ext_phy_ctrl_26;
u32 emif_ddr_ext_phy_ctrl_26_shdw;
u32 emif_ddr_ext_phy_ctrl_27;
u32 emif_ddr_ext_phy_ctrl_27_shdw;
u32 emif_ddr_ext_phy_ctrl_28;
u32 emif_ddr_ext_phy_ctrl_28_shdw;
u32 emif_ddr_ext_phy_ctrl_29;
u32 emif_ddr_ext_phy_ctrl_29_shdw;
u32 emif_ddr_ext_phy_ctrl_30;
u32 emif_ddr_ext_phy_ctrl_30_shdw;
u32 emif_ddr_ext_phy_ctrl_31;
u32 emif_ddr_ext_phy_ctrl_31_shdw;
u32 emif_ddr_ext_phy_ctrl_32;
u32 emif_ddr_ext_phy_ctrl_32_shdw;
u32 emif_ddr_ext_phy_ctrl_33;
u32 emif_ddr_ext_phy_ctrl_33_shdw;
u32 emif_ddr_ext_phy_ctrl_34;
u32 emif_ddr_ext_phy_ctrl_34_shdw;
u32 emif_ddr_ext_phy_ctrl_35;
u32 emif_ddr_ext_phy_ctrl_35_shdw;
union {
u32 emif_ddr_ext_phy_ctrl_36;
u32 emif_ddr_fifo_misaligned_clear_1;
};
union {
u32 emif_ddr_ext_phy_ctrl_36_shdw;
u32 emif_ddr_fifo_misaligned_clear_2;
};
};
struct dmm_lisa_map_regs {
......
......@@ -21,6 +21,7 @@
#include "board.h"
#include <power/pmic.h>
#include <power/tps65218.h>
#include <power/tps62362.h>
#include <miiphy.h>
#include <cpsw.h>
......@@ -81,12 +82,12 @@ static int read_eeprom(struct am43xx_board_id *header)
const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
{ /* 19.2 MHz */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
{125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
{-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
{-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
{125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
{150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
{125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
{625, 11, 1, -1, -1, -1, -1} /* OPP NT */
},
{ /* 24 MHz */
{300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
......@@ -115,24 +116,32 @@ const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
};
const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
{-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
{1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
{1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
{1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
};
const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
{-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
{960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
{960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
{400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
{400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
{384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
{480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
};
const struct dpll_params epos_evm_dpll_ddr = {
266, 24, 1, -1, 1, -1, -1};
const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
{665, 47, 1, -1, 4, -1, -1}, /*19.2*/
{133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
{133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
};
const struct dpll_params gp_evm_dpll_ddr = {
400, 23, 1, -1, 1, -1, -1};
50, 2, 1, -1, 2, -1, -1};
static const struct dpll_params idk_dpll_ddr = {
400, 23, 1, -1, 2, -1, -1
};
const struct ctrl_ioregs ioregs_lpddr2 = {
.cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
......@@ -157,7 +166,7 @@ const struct emif_regs emif_regs_lpddr2 = {
.emif_rd_wr_lvl_rmp_win = 0x0,
.emif_rd_wr_lvl_rmp_ctl = 0x0,
.emif_rd_wr_lvl_ctl = 0x0,
.emif_ddr_phy_ctlr_1 = 0x0E084006,
.emif_ddr_phy_ctlr_1 = 0x0E284006,
.emif_rd_wr_exec_thresh = 0x80000405,
.emif_ddr_ext_phy_ctrl_1 = 0x04010040,
.emif_ddr_ext_phy_ctrl_2 = 0x00500050,
......@@ -170,29 +179,6 @@ const struct emif_regs emif_regs_lpddr2 = {
.emif_cos_config = 0x000FFFFF
};
const u32 ext_phy_ctrl_const_base_lpddr2[] = {
0x00500050,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x40001000,
0x08102040
};
const struct ctrl_ioregs ioregs_ddr3 = {
.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
......@@ -201,7 +187,7 @@ const struct ctrl_ioregs ioregs_ddr3 = {
.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
.emif_sdram_config_ext = 0x0143,
.emif_sdram_config_ext = 0xc163,
};
const struct emif_regs ddr3_emif_regs_400Mhz = {
......@@ -301,150 +287,32 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
.emif_cos_config = 0x000FFFFF
};
const u32 ext_phy_ctrl_const_base_ddr3[] = {
0x00400040,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00340034,
0x00340034,
0x00340034,
0x00340034,
0x00340034,
0x0,
0x0,
0x40000000,
0x08102040
};
const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
0x00000000,
0x00000045,
0x00000046,
0x00000048,
0x00000047,
0x00000000,
0x0000004C,
0x00000070,
0x00000085,
0x000000A3,
0x00000000,
0x0000000C,
0x00000030,
0x00000045,
0x00000063,
0x00000000,
0x0,
0x0,
0x40000000,
0x08102040
};
const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
0x00000000,
0x00000044,
0x00000044,
0x00000046,
0x00000046,
0x00000000,
0x00000059,
0x00000077,
0x00000093,
0x000000A8,
0x00000000,
0x00000019,
0x00000037,
0x00000053,
0x00000068,
0x00000000,
0x0,
0x0,
0x40000000,
0x08102040
};
static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
/* first 5 are taken care by emif_regs */
0x00700070,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00350035,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00150015,
0x00150015,
0x00150015,
0x00150015,
0x00150015,
0x00800080,
0x00800080,
0x40000000,
0x08102040,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
.sdram_config = 0x61a11b32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x00000c30,
.sdram_tim1 = 0xeaaad4db,
.sdram_tim2 = 0x266b7fda,
.sdram_tim3 = 0x107f8678,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x50074be4,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1 = 0x00008009,
.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
.emif_ddr_ext_phy_ctrl_2 = 0x00000040,
.emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
.emif_ddr_ext_phy_ctrl_4 = 0x00000051,
.emif_ddr_ext_phy_ctrl_5 = 0x00000051,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000405,
.emif_prio_class_serv_map = 0x00000000,
.emif_connect_id_serv_1_map = 0x00000000,
.emif_connect_id_serv_2_map = 0x00000000,
.emif_cos_config = 0x00ffffff
};
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
if (board_is_eposevm()) {
*regs = ext_phy_ctrl_const_base_lpddr2;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
} else if (board_is_evm_14_or_later()) {
*regs = ext_phy_ctrl_const_base_ddr3_production;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
} else if (board_is_evm_12_or_later()) {
*regs = ext_phy_ctrl_const_base_ddr3_beta;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
} else if (board_is_gpevm()) {
*regs = ext_phy_ctrl_const_base_ddr3;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
} else if (board_is_sk()) {
*regs = ext_phy_ctrl_const_base_ddr3_sk;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
}
return;
}
const struct dpll_params *get_dpll_ddr_params(void)
{
if (board_is_eposevm())
return &epos_evm_dpll_ddr;
else if (board_is_gpevm() || board_is_sk())
return &gp_evm_dpll_ddr;
printf(" Board '%s' not supported\n", am43xx_board_name);
return NULL;
}
/*
* get_sys_clk_index : returns the index of the sys_clk read from
* ctrl status register. This value is either
......@@ -464,6 +332,22 @@ static u32 get_sys_clk_index(void)
CTRL_SYSBOOT_15_14_SHIFT);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
int ind = get_sys_clk_index();