Commit ac337168 authored by Valentin Longchamp's avatar Valentin Longchamp Committed by York Sun

powerpc: add 2 common dcache assembly functions

This patch defines the 2 flush_dcache_range and invalidate_dcache_range
functions for all the powerpc architecture. Their implementation is
borrowed from the kernel's misc_32.S file and replace the ones from
mpc86xx and ppc4xx since they were equivalent.

This is a fix for the problem introduced by this patch:
http://patchwork.ozlabs.org/patch/448849/Signed-off-by: default avatarValentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: default avatarTom Rini <trini@konsulko.com>
Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
parent e8a7f1c3
......@@ -17,6 +17,3 @@ obj-y += speed.o
obj-$(CONFIG_FSL_DIU_FB) += diu.o
obj-$(CONFIG_CMD_IDE) += ide.o
obj-$(CONFIG_PCI) += pci.o
# Stub implementations of cache management functions for USB
obj-$(CONFIG_USB_EHCI) += cache.o
/*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
*
* This file contains stub implementation of
* invalidate_dcache_range()
* flush_dcache_range()
*
* SPDX-License-Identifier: GPL-2.0+
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
}
......@@ -7,7 +7,6 @@
extra-y = start.o
extra-y += traps.o
obj-y += cache.o
obj-y += io.o
obj-y += firmware_sc_task_bestcomm.impl.o
obj-y += i2c.o
......
/*
* This file contains stub implementation of
* invalidate_dcache_range()
* flush_dcache_range()
*
* SPDX-License-Identifier: GPL-2.0+
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
}
......@@ -35,9 +35,6 @@ obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_PCIE) += pcie.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
# Stub implementations of cache management functions for USB
obj-y += cache.o
ifndef CONFIG_SYS_FSL_DDRC_GEN2
obj-y += spd_sdram.o
endif
......
/*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
*
* This file contains stub implementation of
* invalidate_dcache_range()
* flush_dcache_range()
*
* SPDX-License-Identifier: GPL-2.0+
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
}
......@@ -114,7 +114,4 @@ endif
obj-y += tlb.o
obj-y += traps.o
# Stub implementations of cache management functions for USB
obj-y += cache.o
endif # not minimal
/*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
*
* This file contains stub implementation of
* invalidate_dcache_range()
* flush_dcache_range()
*
* SPDX-License-Identifier: GPL-2.0+
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
}
......@@ -114,51 +114,6 @@ _GLOBAL(clean_dcache_range)
sync /* wait for dcbst's to get to ram */
blr
/*
* Write any modified data cache blocks out to memory
* and invalidate the corresponding instruction cache blocks.
*
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
li r5,CACHE_LINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,LG_CACHE_LINE_SIZE
beqlr
mtctr r4
sync
1: dcbf 0,r3
addi r3,r3,CACHE_LINE_SIZE
bdnz 1b
sync /* wait for dcbf's to get to ram */
blr
/*
* Like above, but invalidate the D-cache. This is used by the 8xx
* to invalidate the cache so the PPC core doesn't get stale data
* from the CPM (no cache snooping here :-).
*
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
li r5,CACHE_LINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,LG_CACHE_LINE_SIZE
beqlr
mtctr r4
sync
1: dcbi 0,r3
addi r3,r3,CACHE_LINE_SIZE
bdnz 1b
sync /* wait for dcbi's to get to ram */
blr
/*
* Flush a particular page from the data cache to RAM.
* Note: this is necessary because the instruction cache does *not*
......
......@@ -73,49 +73,6 @@ _GLOBAL(clean_dcache_range)
sync /* wait for dcbst's to get to ram */
blr
/*
* Write any modified data cache blocks out to memory and invalidate them.
* Does not invalidate the corresponding instruction cache blocks.
*
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
1: dcbf 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
blr
/*
* Like above, but invalidate the D-cache. This is used by the 8xx
* to invalidate the cache so the PPC core doesn't get stale data
* from the CPM (no cache snooping here :-).
*
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
1: dcbi 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbi's to get to ram */
blr
/*
* 40x cores have 8K or 16K dcache and 32 byte line size.
* 44x has a 32K dcache and 32 byte line size.
......
......@@ -9,6 +9,9 @@
#include <config.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbf */
......@@ -54,3 +57,48 @@ ppcDcbz:
ppcSync:
sync
blr
/*
* Write any modified data cache blocks out to memory and invalidate them.
* Does not invalidate the corresponding instruction cache blocks.
*
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
1: dcbf 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
blr
/*
* Like above, but invalidate the D-cache. This is used by the 8xx
* to invalidate the cache so the PPC core doesn't get stale data
* from the CPM (no cache snooping here :-).
*
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
sync
1: dcbi 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbi's to get to ram */
blr
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