Commit ac45bb16 authored by Andreas Bießmann's avatar Andreas Bießmann
Browse files

at91: nand: switch atmel_nand to generic GPIO API


Signed-off-by: default avatarAndreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Tested-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de>
Acked-by: default avatarScott Wood <scottwood@freescale.com>
parent 934e3b52
......@@ -10,6 +10,7 @@
#include <common.h>
#include <asm/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
#include <asm/arch/at91_matrix.h>
......@@ -65,10 +66,10 @@ static void vl_ma2sc_nand_hw_init(void)
/* Configure RDY/BSY */
#ifdef CONFIG_SYS_NAND_READY_PIN
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
#endif
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
......
......@@ -71,6 +71,7 @@
#include <asm/arch/at91_spi.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include "ethernut5_pwrman.h"
......@@ -141,7 +142,7 @@ static void ethernut5_nand_hw_init(void)
/* Ready pin is optional. */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
#endif
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
......
......@@ -12,6 +12,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
......@@ -74,10 +75,10 @@ static void meesc_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif /* CONFIG_CMD_NAND */
......
......@@ -12,6 +12,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
......@@ -82,10 +83,10 @@ static void otc570_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif /* CONFIG_CMD_NAND */
......
......@@ -12,6 +12,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9260.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
......@@ -78,10 +79,10 @@ static void cpu9260_nand_hw_init(void)
writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
......
......@@ -11,6 +11,7 @@
#include <common.h>
#include <asm/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
......@@ -73,10 +74,10 @@ static void pm9261_nand_hw_init(void)
&pmc->pcer);
/* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
......
......@@ -11,6 +11,7 @@
#include <common.h>
#include <asm/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
......@@ -67,10 +68,10 @@ static void pm9263_nand_hw_init(void)
&smc->cs[3].mode);
/* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
......
......@@ -14,6 +14,7 @@
#include <common.h>
#include <asm/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
......@@ -66,11 +67,11 @@ static void pm9g45_nand_hw_init(void)
#ifdef CONFIG_SYS_NAND_READY_PIN
/* Configure RDY/BSY */
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
#endif
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
......
......@@ -12,9 +12,8 @@
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <malloc.h>
#include <nand.h>
......@@ -1146,8 +1145,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
#ifdef CONFIG_SYS_NAND_ENABLE_PIN
at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
!(ctrl & NAND_NCE));
gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
#endif
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
......@@ -1159,7 +1157,7 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
#ifdef CONFIG_SYS_NAND_READY_PIN
static int at91_nand_ready(struct mtd_info *mtd)
{
return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
}
#endif
......
......@@ -113,8 +113,8 @@
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 5
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
......
......@@ -280,8 +280,8 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13)
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
......
......@@ -149,7 +149,7 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#endif
/* JFFS2 */
......
......@@ -143,8 +143,8 @@
# define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
# define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
# define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22
# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
#endif
/* Ethernet */
......
......@@ -193,8 +193,8 @@
# define CONFIG_SYS_NAND_DBW_8
# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
# define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
# define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22
# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
#endif
/* Ethernet */
......
......@@ -219,8 +219,8 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 16
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
/* NOR flash */
#define CONFIG_SYS_FLASH_CFI 1
......
......@@ -241,8 +241,8 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30)
#endif
......
......@@ -106,8 +106,8 @@
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 3
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3)
#endif
......
......@@ -320,8 +320,8 @@
#define CONFIG_SYS_NAND_DBW_8 1
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0)
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
......
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